| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 |
| # RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -run-pass=si-insert-waitcnts -amdgpu-expert-scheduling-mode -o - %s | FileCheck %s |
| |
| --- |
| name: soft_wait_before_s_barrier |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_before_s_barrier |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_1 |
| ; CHECK-NEXT: renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_BARRIER_SIGNAL_IMM -1 |
| ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_1 |
| ; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1 |
| |
| renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| $vcc_lo = S_MOV_B32 $exec_lo |
| renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| |
| bb.1: |
| successors: %bb.2, %bb.1 |
| liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| |
| S_WAIT_DSCNT_soft 0 |
| S_BARRIER_SIGNAL_IMM -1 |
| $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc |
| |
| bb.2: |
| S_ENDPGM 0 |
| ... |
| |
| --- |
| name: soft_wait_multipath_first_pred_needs_wait |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_multipath_first_pred_needs_wait |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: liveins: $sgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_0 |
| ; CHECK-NEXT: $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 42, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: S_BARRIER_SIGNAL_IMM -1 |
| ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| liveins: $sgpr0 |
| |
| $vgpr0 = V_MOV_B32_e32 0, implicit $exec |
| S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| S_CBRANCH_SCC1 %bb.2, implicit $scc |
| |
| bb.1: |
| successors: %bb.3(0x80000000) |
| liveins: $vgpr0 |
| |
| $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| S_BRANCH %bb.3 |
| |
| bb.2: |
| successors: %bb.3(0x80000000) |
| liveins: $vgpr0 |
| |
| $vgpr1 = V_MOV_B32_e32 42, implicit $exec |
| |
| bb.3: |
| liveins: $vgpr0, $vgpr1 |
| |
| S_WAIT_DSCNT_soft 0 |
| S_BARRIER_SIGNAL_IMM -1 |
| $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec |
| S_ENDPGM 0 |
| ... |
| |
| --- |
| name: soft_wait_second_pred_needs_wait |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_second_pred_needs_wait |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: liveins: $sgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 42, implicit $exec |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_0 |
| ; CHECK-NEXT: $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| liveins: $sgpr0 |
| |
| $vgpr0 = V_MOV_B32_e32 0, implicit $exec |
| S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| S_CBRANCH_SCC1 %bb.2, implicit $scc |
| |
| bb.1: |
| successors: %bb.3(0x80000000) |
| liveins: $vgpr0 |
| |
| $vgpr1 = V_MOV_B32_e32 42, implicit $exec |
| S_BRANCH %bb.3 |
| |
| bb.2: |
| successors: %bb.3(0x80000000) |
| liveins: $vgpr0 |
| |
| $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| |
| bb.3: |
| liveins: $vgpr0, $vgpr1 |
| |
| S_WAIT_DSCNT_soft 0 |
| $vgpr2 = V_MOV_B32_e32 $vgpr1, implicit $exec |
| S_ENDPGM 0 |
| ... |
| |
| # Test that soft wait in RequiredWait does not incorrectly simplify VM_VSRC. |
| # When processing from the path without DS operations first: |
| # - soft S_WAIT_DSCNT goes to RequiredWait (AllowWaitDeletion=false) |
| # - hard S_WAITCNT_DEPCTR with VM_VSRC=0 goes to Wait |
| # If we incorrectly used RequiredWait in simplifyVmVsrc's CheckWait, |
| # the VM_VSRC would be simplified away because DS_CNT=0 is present. |
| # Then when the soft wait is deleted (not needed from second path), |
| # we'd lose the required VM_VSRC wait. |
| --- |
| name: soft_wait_does_not_simplify_vm_vsrc |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_does_not_simplify_vm_vsrc |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| ; CHECK-NEXT: liveins: $sgpr0, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_BRANCH %bb.3 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: successors: %bb.3(0x80000000) |
| ; CHECK-NEXT: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_LOAD_V4_V1_gfx12 $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.3: |
| ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0 |
| ; CHECK-NEXT: S_WAIT_LOADCNT_DSCNT .Loadcnt_0_Dscnt_0 |
| ; CHECK-NEXT: $vgpr4 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| liveins: $sgpr0, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0 |
| |
| S_CMP_EQ_U32 $sgpr0, 0, implicit-def $scc |
| S_CBRANCH_SCC1 %bb.2, implicit $scc |
| |
| bb.1: |
| successors: %bb.3(0x80000000) |
| liveins: $vgpr0 |
| |
| ; DS operation - requires DS_CNT wait |
| $vgpr1 = DS_READ_B32_gfx9 $vgpr0, 0, 0, implicit $exec |
| S_BRANCH %bb.3 |
| |
| bb.2: |
| successors: %bb.3(0x80000000) |
| liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $vgpr0 |
| |
| $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_LOAD_V4_V1_gfx12 $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8) |
| |
| bb.3: |
| liveins: $vgpr0, $vgpr1 |
| |
| S_WAIT_DSCNT_soft 0 |
| S_WAITCNT_DEPCTR .VmVsrc_0 |
| $vgpr4 = V_ADD_F32_e32 $vgpr0, $vgpr1, implicit $mode, implicit $exec |
| S_ENDPGM 0 |
| ... |
| |
| --- |
| name: soft_wait_no_vmsrc_simplify |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_no_vmsrc_simplify |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_1 |
| ; CHECK-NEXT: renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_0 |
| ; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0 |
| ; CHECK-NEXT: $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| ; CHECK-NEXT: S_BARRIER_SIGNAL_IMM -1 |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1 |
| |
| renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| $vcc_lo = S_MOV_B32 $exec_lo |
| renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| |
| bb.1: |
| successors: %bb.2, %bb.1 |
| liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| S_WAIT_DSCNT_soft 0 |
| $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| S_BARRIER_SIGNAL_IMM -1 |
| S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc |
| |
| bb.2: |
| S_ENDPGM 0 |
| ... |
| |
| --- |
| name: soft_wait_no_vmsrc_simplify2 |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_no_vmsrc_simplify2 |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_1 |
| ; CHECK-NEXT: renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0 |
| ; CHECK-NEXT: $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| ; CHECK-NEXT: S_BARRIER_SIGNAL_IMM -1 |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_0 |
| ; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1 |
| |
| renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| $vcc_lo = S_MOV_B32 $exec_lo |
| renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| |
| bb.1: |
| successors: %bb.2, %bb.1 |
| liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| S_WAIT_DSCNT_soft 0 |
| $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| S_BARRIER_SIGNAL_IMM -1 |
| GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc |
| |
| bb.2: |
| S_ENDPGM 0 |
| ... |
| |
| --- |
| name: soft_wait_promote_simplify |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| body: | |
| ; CHECK-LABEL: name: soft_wait_promote_simplify |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.1(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0 |
| ; CHECK-NEXT: V_NOP_e32 implicit $exec |
| ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec |
| ; CHECK-NEXT: S_SETREG_IMM32_B32 2, 2074, implicit-def $mode, implicit $mode |
| ; CHECK-NEXT: renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| ; CHECK-NEXT: renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_1 |
| ; CHECK-NEXT: renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: S_WAIT_DSCNT 0 |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0 |
| ; CHECK-NEXT: $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| ; CHECK-NEXT: S_BARRIER_SIGNAL_IMM -1 |
| ; CHECK-NEXT: S_WAITCNT_DEPCTR .VaVdst_0 |
| ; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| ; CHECK-NEXT: renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc_lo |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| successors: %bb.1 |
| |
| renamable $vgpr17 = V_MOV_B32_e32 0, implicit $exec |
| renamable $vgpr32_vgpr33 = V_MOV_B64_e32 0, implicit $exec |
| $vcc_lo = S_MOV_B32 $exec_lo |
| renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| |
| bb.1: |
| successors: %bb.2, %bb.1 |
| liveins: $vgpr32_vgpr33, $vgpr17, $vgpr0, $vcc_lo |
| S_WAIT_DSCNT_soft 0 |
| $vgpr17 = V_MOV_B32_e32 $vgpr0, implicit $exec |
| S_BARRIER_SIGNAL_IMM -1 |
| GLOBAL_LOAD_ASYNC_TO_LDS_B64 $vgpr17, $vgpr32_vgpr33, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt |
| renamable $vgpr0 = DS_READ_B32_gfx9 renamable $vgpr17, 0, 0, implicit $exec |
| S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo, implicit $vcc |
| |
| bb.2: |
| S_ENDPGM 0 |
| ... |
