llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s

define i32 @select.hi32.sgpr.eq(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.eq:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_eq_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.eq.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.eq.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.eq.multiuse(i64 inreg %mask, i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
; CHECK-LABEL: select.hi32.sgpr.eq.multiuse:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_eq_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    s_cselect_b32 s5, s20, s21
; CHECK-NEXT:    s_add_i32 s4, s4, s5
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, u0xa0a0a0a000000000
  %ab = select i1 %mask.hi.c, i32 %a, i32 %b
  %cd = select i1 %mask.hi.c, i32 %c, i32 %d
  %ret = add i32 %ab, %cd
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ne(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ne:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lg_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ne i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ne.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ne.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_ne_u64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ne i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ult.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ult.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ult.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ult.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_u32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ult.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ult.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.slt.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.slt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_i32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.slt.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.slt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_i32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.slt.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.slt.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.uge.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.uge.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_u32 s4, 0xa0a0a09f
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.uge.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.uge.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.uge.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.uge.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_ge_u64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sge.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sge.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_i32 s4, 0xa0a0a09f
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sge.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sge.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_i32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sge.bad(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sge.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s18
; CHECK-NEXT:    v_mov_b32_e32 v1, s19
; CHECK-NEXT:    s_and_b32 s5, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    v_cmp_ge_i64_e32 vcc, s[4:5], v[0:1]
; CHECK-NEXT:    s_and_b64 s[4:5], vcc, exec
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ugt.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ugt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ugt.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ugt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_u32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ugt.2(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ugt.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_u32 s4, s19
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sgt.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sgt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_i32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sgt.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sgt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_i32 s4, 0xa0a0a0a0
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sgt.2(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sgt.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_gt_i32 s4, s19
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ule.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ule.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_u32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ule.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ule.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_u32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.ule.2(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.ule.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_le_u32 s4, s19
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sle.0(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sle.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_i32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sle.1(i64 inreg %mask, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sle.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_lt_i32 s4, 0xa0a0a0a1
; CHECK-NEXT:    s_cselect_b32 s4, s18, s19
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.sgpr.sle.2(i64 inreg %mask, i64 inreg %cmp, i32 inreg %a, i32 inreg %b) {
; CHECK-LABEL: select.hi32.sgpr.sle.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_and_b32 s4, s17, 0xaaaaaaaa
; CHECK-NEXT:    s_cmp_le_i32 s4, s19
; CHECK-NEXT:    s_cselect_b32 s4, s20, s21
; CHECK-NEXT:    v_mov_b32_e32 v0, s4
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.eq(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.eq:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.eq.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.eq.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_eq_u64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.eq.multiuse(i64 %mask, i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: select.hi32.vgpr.eq.multiuse:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    v_cndmask_b32_e32 v1, v5, v4, vcc
; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp eq i64 %mask.hi, u0xa0a0a0a000000000
  %ab = select i1 %mask.hi.c, i32 %a, i32 %b
  %cd = select i1 %mask.hi.c, i32 %c, i32 %d
  %ret = add i32 %ab, %cd
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ne(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ne:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ne i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ne.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ne.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_ne_u64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ne i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sge.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sge.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a09f
; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sge.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sge.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sge.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sge.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_ge_i64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sge i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.slt.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.slt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.slt.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.slt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.slt.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.slt.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp slt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.uge.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.uge.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a09f
; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.uge.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.uge.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.uge.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.uge.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_ge_u64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp uge i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ult.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ult.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ult.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ult.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ult.bad(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ult.bad:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v1, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ult i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ugt.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ugt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ugt.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ugt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ugt.2(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ugt.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc, v0, v3
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ugt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sgt.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sgt.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sgt.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sgt.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a0
; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sgt.2(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sgt.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc, v0, v3
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sgt i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ule.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ule.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ule.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ule.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.ule.2(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.ule.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, v0, v3
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp ule i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sle.0(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sle.0:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, u0xa0a0a0a000000000
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sle.1(i64 %mask, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sle.1:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    s_mov_b32 s4, 0xa0a0a0a1
; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc, s4, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, u0xa0a0a0a000000001
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}

define i32 @select.hi32.vgpr.sle.2(i64 %mask, i64 %cmp, i32 %a, i32 %b) {
; CHECK-LABEL: select.hi32.vgpr.sle.2:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_and_b32_e32 v0, 0xaaaaaaaa, v1
; CHECK-NEXT:    v_cmp_le_i32_e32 vcc, v0, v3
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %mask.hi = and i64 %mask, u0xaaaaaaaa00000000
  %mask.hi.c = icmp sle i64 %mask.hi, %cmp
  %ret = select i1 %mask.hi.c, i32 %a, i32 %b
  ret i32 %ret
}