llvm/test/CodeGen/AMDGPU/select-bit-test.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck -check-prefix=GFX942 %s
; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX11 %s

define i32 @select_trunc_bit0(i32 %x, i32 %y) {
; GFX942-LABEL: select_trunc_bit0:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_bit0:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %t = trunc i32 %x to i1
  %s = select i1 %t, i32 %y, i32 0
  ret i32 %s
}

define i32 @select_trunc_bit5(i32 %x, i32 %y) {
; GFX942-LABEL: select_trunc_bit5:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_bit5:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %sh = lshr i32 %x, 5
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i32 %y, i32 0
  ret i32 %s
}

define i32 @select_trunc_bit31(i32 %x, i32 %y) {
; GFX942-LABEL: select_trunc_bit31:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 0x80000000, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_bit31:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 0x80000000, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %sh = lshr i32 %x, 31
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i32 %y, i32 0
  ret i32 %s
}

define i32 @select_and_ne_bit6(i32 %x, i32 %y) {
; GFX942-LABEL: select_and_ne_bit6:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 64, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_and_ne_bit6:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 64, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %a = and i32 %x, 64
  %c = icmp ne i32 %a, 0
  %s = select i1 %c, i32 %y, i32 0
  ret i32 %s
}

; The zero is in the true operand.
define i32 @select_trunc_bit5_inverted(i32 %x, i32 %y) {
; GFX942-LABEL: select_trunc_bit5_inverted:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_bit5_inverted:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %sh = lshr i32 %x, 5
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i32 0, i32 %y
  ret i32 %s
}

; A uniform bit test uses s_bitcmp1_b32 + s_cselect_b32.
define amdgpu_kernel void @select_trunc_bit5_uniform(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX942-LABEL: select_trunc_bit5_uniform:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    s_bitcmp1_b32 s2, 5
; GFX942-NEXT:    s_cselect_b32 s2, s3, 0
; GFX942-NEXT:    v_mov_b32_e32 v1, s2
; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX942-NEXT:    s_endpgm
;
; GFX11-LABEL: select_trunc_bit5_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    s_bitcmp1_b32 s2, 5
; GFX11-NEXT:    s_cselect_b32 s2, s3, 0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT:    s_endpgm
  %sh = lshr i32 %x, 5
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i32 %y, i32 0
  store i32 %s, ptr addrspace(1) %out
  ret void
}

; The tested bit is not constant.
define i32 @select_trunc_variable_bit(i32 %x, i32 %n, i32 %y) {
; GFX942-LABEL: select_trunc_variable_bit:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_variable_bit:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_and_b32_e32 v0, 1, v0
; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %sh = lshr i32 %x, %n
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i32 %y, i32 0
  ret i32 %s
}

define i64 @select_trunc_bit5_i64(i32 %x, i64 %y) {
; GFX942-LABEL: select_trunc_bit5_i64:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; GFX942-NEXT:    s_nop 1
; GFX942-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX942-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX942-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: select_trunc_bit5_i64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_and_b32_e32 v0, 32, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    v_dual_cndmask_b32 v0, 0, v1 :: v_dual_cndmask_b32 v1, 0, v2
; GFX11-NEXT:    s_setpc_b64 s[30:31]
  %sh = lshr i32 %x, 5
  %t = trunc i32 %sh to i1
  %s = select i1 %t, i64 %y, i64 0
  ret i64 %s
}