llvm/test/CodeGen/AMDGPU/regcoalesce-64-bit-only-regs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s

# These SRC_*_HI registers do not exist, make sure coalescer does not use it.

---
name:            src_private_base
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: src_private_base
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $src_private_base
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; CHECK-NEXT: $scc = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]].sub1, [[DEF]].sub1, implicit-def dead $scc, implicit killed $scc
    %0:sreg_64 = COPY $src_private_base
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %2:sreg_32 = S_SUBB_U32 killed %0.sub1:sreg_64, %1.sub1:sreg_64, implicit-def dead $scc, implicit killed $scc
...

---
name:            src_private_limit
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: src_private_limit
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $src_private_limit
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; CHECK-NEXT: $scc = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]].sub1, [[DEF]].sub1, implicit-def dead $scc, implicit killed $scc
    %0:sreg_64 = COPY $src_private_limit
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %2:sreg_32 = S_SUBB_U32 killed %0.sub1:sreg_64, %1.sub1:sreg_64, implicit-def dead $scc, implicit killed $scc
...

---
name:            src_shared_base
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: src_shared_base
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $src_shared_base
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; CHECK-NEXT: $scc = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]].sub1, [[DEF]].sub1, implicit-def dead $scc, implicit killed $scc
    %0:sreg_64 = COPY $src_shared_base
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %2:sreg_32 = S_SUBB_U32 killed %0.sub1:sreg_64, %1.sub1:sreg_64, implicit-def dead $scc, implicit killed $scc
...

---
name:            src_shared_limit
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: src_shared_limit
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $src_shared_limit
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; CHECK-NEXT: $scc = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]].sub1, [[DEF]].sub1, implicit-def dead $scc, implicit killed $scc
    %0:sreg_64 = COPY $src_shared_limit
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %2:sreg_32 = S_SUBB_U32 killed %0.sub1:sreg_64, %1.sub1:sreg_64, implicit-def dead $scc, implicit killed $scc
...