llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s

# Test that the buildSpillLoadStore does correct calculations for Maxoffset in case of
# spill instructions. Must emit offset within 13 bit signed number range.

---
name:            test_spill_v6_offset_overflow
tracksRegLiveness: true
fixedStack:
  - { id: 0, type: spill-slot, offset: 4084, size: 24, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:           []
machineFunctionInfo:
  hasSpilledVGPRs: true
  stackPtrOffsetReg: '$sgpr32'
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5

    ; CHECK-LABEL: name: test_spill_v6_offset_overflow
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $sgpr0 = S_ADD_I32 $sgpr32, 4084, implicit-def dead $scc
    ; CHECK-NEXT: SCRATCH_STORE_DWORDX4_SADDR $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %fixed-stack.0, align 4, addrspace 5)
    ; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR $vgpr4_vgpr5, killed $sgpr0, 16, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %fixed-stack.0 + 16, align 4, addrspace 5)
    ; CHECK-NEXT: S_ENDPGM 0
    SI_SPILL_AV192_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %fixed-stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %fixed-stack.0, align 4, addrspace 5)
    S_ENDPGM 0

...