llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1251 < %s | FileCheck %s

define <2 x i64> @func_v2i64_vector(<2 x i64> %arg) {
; CHECK-LABEL: func_v2i64_vector:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    v_lshlrev_b64_e32 v[0:1], 32, v[0:1]
; CHECK-NEXT:    v_lshlrev_b64_e32 v[2:3], 31, v[2:3]
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %i = shl <2 x i64> %arg, <i64 32, i64 31>
  ret <2 x i64> %i
}

define amdgpu_ps <2 x i64> @func_v2i64_scalar(<2 x i64> inreg %arg) {
; CHECK-LABEL: func_v2i64_scalar:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    global_wb
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_lshl_b64 s[0:1], s[0:1], 32
; CHECK-NEXT:    s_lshl_b64 s[2:3], s[2:3], 31
; CHECK-NEXT:    ; return to shader part epilog
  %i = shl <2 x i64> %arg, <i64 32, i64 31>
  ret <2 x i64> %i
}

define <4 x i64> @func_4xi64_vector(<4 x i64> %arg) {
; CHECK-LABEL: func_4xi64_vector:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v1, v0
; CHECK-NEXT:    v_lshlrev_b64_e32 v[6:7], 31, v[6:7]
; CHECK-NEXT:    v_lshlrev_b64_e32 v[4:5], 32, v[4:5]
; CHECK-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 0
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %i = shl <4 x i64> %arg, <i64 32, i64 32, i64 32, i64 31>
  ret <4 x i64> %i
}

define amdgpu_ps <4 x i64> @func_4xi64_scalar(<4 x i64> inreg %arg) {
; CHECK-LABEL: func_4xi64_scalar:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    global_wb
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b32 s3, s2
; CHECK-NEXT:    s_mov_b32 s1, s0
; CHECK-NEXT:    s_lshl_b64 s[6:7], s[6:7], 31
; CHECK-NEXT:    s_lshl_b64 s[4:5], s[4:5], 32
; CHECK-NEXT:    s_mov_b32 s0, 0
; CHECK-NEXT:    s_mov_b32 s2, 0
; CHECK-NEXT:    ; return to shader part epilog
  %i = shl <4 x i64> %arg, <i64 32, i64 32, i64 32, i64 31>
  ret <4 x i64> %i
}

define <8 x i64> @func_8xi64_vector(<8 x i64> %arg) {
; CHECK-LABEL: func_8xi64_vector:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v9, v8
; CHECK-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v5, v4
; CHECK-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v1, v0
; CHECK-NEXT:    v_lshlrev_b64_e32 v[14:15], 31, v[14:15]
; CHECK-NEXT:    v_lshlrev_b64_e32 v[12:13], 32, v[12:13]
; CHECK-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 0
; CHECK-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 0
; CHECK-NEXT:    v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v10, 0
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %i = shl <8 x i64> %arg, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 31>
  ret <8 x i64> %i
}

define amdgpu_ps <8 x i64> @func_8xi64_scalar(<8 x i64> inreg %arg) {
; CHECK-LABEL: func_8xi64_scalar:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    global_wb
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b32 s11, s10
; CHECK-NEXT:    s_mov_b32 s9, s8
; CHECK-NEXT:    s_mov_b32 s7, s6
; CHECK-NEXT:    s_mov_b32 s5, s4
; CHECK-NEXT:    s_mov_b32 s3, s2
; CHECK-NEXT:    s_mov_b32 s1, s0
; CHECK-NEXT:    s_lshl_b64 s[14:15], s[14:15], 31
; CHECK-NEXT:    s_lshl_b64 s[12:13], s[12:13], 32
; CHECK-NEXT:    s_mov_b32 s0, 0
; CHECK-NEXT:    s_mov_b32 s2, 0
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mov_b32 s8, 0
; CHECK-NEXT:    s_mov_b32 s10, 0
; CHECK-NEXT:    ; return to shader part epilog
  %i = shl <8 x i64> %arg, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 31>
  ret <8 x i64> %i
}

define <16 x i64> @func_16xi64_vector(<16 x i64> %arg) {
; CHECK-LABEL: func_16xi64_vector:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    scratch_load_b32 v31, off, s32
; CHECK-NEXT:    v_dual_mov_b32 v27, v26 :: v_dual_mov_b32 v25, v24
; CHECK-NEXT:    v_dual_mov_b32 v23, v22 :: v_dual_mov_b32 v21, v20
; CHECK-NEXT:    v_dual_mov_b32 v19, v18 :: v_dual_mov_b32 v17, v16
; CHECK-NEXT:    v_dual_mov_b32 v15, v14 :: v_dual_mov_b32 v13, v12
; CHECK-NEXT:    v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v9, v8
; CHECK-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v5, v4
; CHECK-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v1, v0
; CHECK-NEXT:    v_lshlrev_b64_e32 v[28:29], 32, v[28:29]
; CHECK-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 0
; CHECK-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 0
; CHECK-NEXT:    v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v10, 0
; CHECK-NEXT:    v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v14, 0
; CHECK-NEXT:    v_dual_mov_b32 v16, 0 :: v_dual_mov_b32 v18, 0
; CHECK-NEXT:    v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v22, 0
; CHECK-NEXT:    v_dual_mov_b32 v24, 0 :: v_dual_mov_b32 v26, 0
; CHECK-NEXT:    s_wait_loadcnt 0x0
; CHECK-NEXT:    v_lshlrev_b64_e32 v[30:31], 31, v[30:31]
; CHECK-NEXT:    s_set_pc_i64 s[30:31]
  %i = shl <16 x i64> %arg, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 31>
  ret <16 x i64> %i
}

define amdgpu_ps <16 x i64> @func_16xi64_scalar(<16 x i64> inreg %arg) {
; CHECK-LABEL: func_16xi64_scalar:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    global_wb
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b32 s27, s26
; CHECK-NEXT:    s_mov_b32 s25, s24
; CHECK-NEXT:    s_mov_b32 s23, s22
; CHECK-NEXT:    s_mov_b32 s21, s20
; CHECK-NEXT:    s_mov_b32 s19, s18
; CHECK-NEXT:    s_mov_b32 s17, s16
; CHECK-NEXT:    s_mov_b32 s15, s14
; CHECK-NEXT:    s_mov_b32 s13, s12
; CHECK-NEXT:    s_mov_b32 s11, s10
; CHECK-NEXT:    s_mov_b32 s9, s8
; CHECK-NEXT:    s_mov_b32 s7, s6
; CHECK-NEXT:    s_mov_b32 s5, s4
; CHECK-NEXT:    s_mov_b32 s3, s2
; CHECK-NEXT:    s_mov_b32 s1, s0
; CHECK-NEXT:    s_lshl_b64 s[30:31], s[30:31], 31
; CHECK-NEXT:    s_lshl_b64 s[28:29], s[28:29], 32
; CHECK-NEXT:    s_mov_b32 s0, 0
; CHECK-NEXT:    s_mov_b32 s2, 0
; CHECK-NEXT:    s_mov_b32 s4, 0
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mov_b32 s8, 0
; CHECK-NEXT:    s_mov_b32 s10, 0
; CHECK-NEXT:    s_mov_b32 s12, 0
; CHECK-NEXT:    s_mov_b32 s14, 0
; CHECK-NEXT:    s_mov_b32 s16, 0
; CHECK-NEXT:    s_mov_b32 s18, 0
; CHECK-NEXT:    s_mov_b32 s20, 0
; CHECK-NEXT:    s_mov_b32 s22, 0
; CHECK-NEXT:    s_mov_b32 s24, 0
; CHECK-NEXT:    s_mov_b32 s26, 0
; CHECK-NEXT:    ; return to shader part epilog
  %i = shl <16 x i64> %arg, <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 31>
  ret <16 x i64> %i
}