llvm/test/CodeGen/AMDGPU/mode-register-call-boundary.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s

; SIModeRegister restores the default mode at a call or a return, unless the
; program asked for the mode itself.

declare void @sink(float)
declare float @tail_target(float)

define float @ret_restores_default(double %a) {
; CHECK-LABEL: ret_restores_default:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  ret float %t
}

define float @tail_call_restores_default(double %a) {
; CHECK-LABEL: tail_call_restores_default:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_getpc_b64 s[16:17]
; CHECK-NEXT:    s_add_u32 s16, s16, tail_target@gotpcrel32@lo+4
; CHECK-NEXT:    s_addc_u32 s17, s17, tail_target@gotpcrel32@hi+12
; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[16:17], 0x0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; CHECK-NEXT:    s_setpc_b64 s[16:17]
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  %u = tail call float @tail_target(float %t)
  ret float %u
}

define void @call_restores_default(double %a) {
; CHECK-LABEL: call_restores_default:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s16, s33
; CHECK-NEXT:    s_mov_b32 s33, s32
; CHECK-NEXT:    s_or_saveexec_b64 s[18:19], -1
; CHECK-NEXT:    buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
; CHECK-NEXT:    s_mov_b64 exec, s[18:19]
; CHECK-NEXT:    v_writelane_b32 v40, s16, 2
; CHECK-NEXT:    v_writelane_b32 v40, s30, 0
; CHECK-NEXT:    s_addk_i32 s32, 0x400
; CHECK-NEXT:    v_writelane_b32 v40, s31, 1
; CHECK-NEXT:    s_getpc_b64 s[16:17]
; CHECK-NEXT:    s_add_u32 s16, s16, sink@gotpcrel32@lo+4
; CHECK-NEXT:    s_addc_u32 s17, s17, sink@gotpcrel32@hi+12
; CHECK-NEXT:    s_load_dwordx2 s[16:17], s[16:17], 0x0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; CHECK-NEXT:    s_swappc_b64 s[30:31], s[16:17]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_readlane_b32 s30, v40, 0
; CHECK-NEXT:    v_readlane_b32 s31, v40, 1
; CHECK-NEXT:    s_mov_b32 s32, s33
; CHECK-NEXT:    v_readlane_b32 s4, v40, 2
; CHECK-NEXT:    s_or_saveexec_b64 s[6:7], -1
; CHECK-NEXT:    buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
; CHECK-NEXT:    s_mov_b64 exec, s[6:7]
; CHECK-NEXT:    s_mov_b32 s33, s4
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  call void @sink(float %t)
  ret void
}

; s_endpgm ends the wave, so there is no caller to restore for.
define amdgpu_kernel void @kernel_no_restore(ptr addrspace(1) %out, double %a) {
; CHECK-LABEL: kernel_no_restore:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v0, s2
; CHECK-NEXT:    v_mov_b32_e32 v1, s3
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    global_store_dword v2, v0, s[0:1]
; CHECK-NEXT:    s_endpgm
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  store float %t, ptr addrspace(1) %out
  ret void
}

; A return to the shader epilog is still a return to external code.
define amdgpu_gs float @gs_restores_default(double %a) {
; CHECK-LABEL: gs_restores_default:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; CHECK-NEXT:    ; return to shader part epilog
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  ret float %t
}

define float @explicit_setreg_persists_with_fptrunc_round(double %a) {
; CHECK-LABEL: explicit_setreg_persists_with_fptrunc_round:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
; CHECK-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %t = call float @llvm.fptrunc.round.f32.f64(double %a, metadata !"round.upward")
  call void @llvm.set.rounding(i32 0)
  ret float %t
}