llvm/test/CodeGen/AMDGPU/mfma-no-multiple-copies.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -run-pass=machine-scheduler -amdgpu-disable-rewrite-mfma-form-sched-stage=false %s -o - | FileCheck %s

# Test that only one copy generated for all users of mfma in the same block.

--- |
  define amdgpu_kernel void @mfma_no_multiple_copies() #0 { ret void }
  attributes #0 = { "amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64" }
...

---
name: mfma_no_multiple_copies
tracksRegLiveness: true
machineFunctionInfo:
  isEntryFunction: true
body: |
  ; CHECK-LABEL: name: mfma_no_multiple_copies
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %p0:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %m3:vreg_128_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:areg_128_align2 = COPY %m3
  ; CHECK-NEXT:   %p1:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p2:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p3:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p4:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p5:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p6:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   %p7:vreg_1024 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %m0:areg_128_align2 = V_MFMA_F32_16X16X32_F16_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   %m1:areg_128_align2 = V_MFMA_F32_16X16X32_F16_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m0, 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   %m2:areg_128_align2 = V_MFMA_F32_16X16X32_F16_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m1, 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit undef $scc
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   KILL %p0, %p1, %p2, %p3, %p4, %p5, %p6, %p7
  ; CHECK-NEXT:   %m4:areg_128_align2 = V_MFMA_F32_16X16X32_F16_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m2, 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_128_align2 = COPY %m4
  ; CHECK-NEXT:   %out1:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   %out2:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s1:vreg_128_align2, undef %s0:vreg_128_align2, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0, implicit %out1, implicit %out2
  bb.0:
    successors: %bb.1(0x80000000)
    %p0:vreg_1024 = IMPLICIT_DEF
    %p1:vreg_1024 = IMPLICIT_DEF
    %p2:vreg_1024 = IMPLICIT_DEF
    %p3:vreg_1024 = IMPLICIT_DEF
    %p4:vreg_1024 = IMPLICIT_DEF
    %p5:vreg_1024 = IMPLICIT_DEF
    %p6:vreg_1024 = IMPLICIT_DEF
    %p7:vreg_1024 = IMPLICIT_DEF

    %m3:vreg_128_align2 = IMPLICIT_DEF

    S_BRANCH %bb.1

  bb.1:
    successors: %bb.1(0x7c000000), %bb.2(0x04000000)

    %m0:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m3, 0, 0, 0, implicit $mode, implicit $exec
    %m1:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m0, 0, 0, 0, implicit $mode, implicit $exec
    %m2:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m1, 0, 0, 0, implicit $mode, implicit $exec

    S_CBRANCH_SCC1 %bb.2, implicit undef $scc
    S_BRANCH %bb.1

  bb.2:

    %m4:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m2, 0, 0, 0, implicit $mode, implicit $exec

    %out1:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s0:vreg_128_align2, undef %s1:vreg_128_align2, %m4, 0, 0, 0, implicit $mode, implicit $exec
    %out2:vreg_128_align2 = V_MFMA_F32_16X16X32_F16_vgprcd_e64 undef %s1:vreg_128_align2, undef %s0:vreg_128_align2, %m4, 0, 0, 0, implicit $mode, implicit $exec

    KILL %p0, %p1, %p2, %p3, %p4, %p5, %p6, %p7

    S_ENDPGM 0, implicit %out1, implicit %out2
...