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llvm/llvm-project.git/refs/heads/main/./llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
blob: 9b99d6fa5bb1d632a136e3d3f7274d26e25f4172 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=STRICT
;; Note: unaligned-access-mode is default on HSA targets
; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=UNALIGNED_ONLY
; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=RELAXED_OOB_ONLY
; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=BOTH_FLAGS
target triple = "amdgcn--"
define i32 @load_i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
; STRICT-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret i32 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i32 @load_i32_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret i32 [[RET]]
;
; BOTH_FLAGS-LABEL: define i32 @load_i32_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i32 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i32, ptr addrspace(7) %q, align 4
ret i32 %ret
}
define void @store_i32_align4(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align4(
; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i32_align4(
; UNALIGNED_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align4(
; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i32_align4(
; BOTH_FLAGS-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i32 %data, ptr addrspace(7) %q, align 4
ret void
}
define i32 @load_i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; STRICT-NEXT: [[RET:%.*]] = bitcast <2 x i16> [[RET_SLICE_1]] to i32
; STRICT-NEXT: ret i32 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i32 @load_i32_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i16> [[RET_SLICE_1]] to i32
; RELAXED_OOB_ONLY-NEXT: ret i32 [[RET]]
;
; BOTH_FLAGS-LABEL: define i32 @load_i32_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i32 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i32, ptr addrspace(7) %q, align 2
ret i32 %ret
}
define void @store_i32_align2(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align2(
; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <2 x i16>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i32_align2(
; UNALIGNED_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align2(
; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <2 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i32_align2(
; BOTH_FLAGS-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i32 %data, ptr addrspace(7) %q, align 2
ret void
}
define i32 @load_i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[RET:%.*]] = bitcast <4 x i8> [[RET_SLICE_3]] to i32
; STRICT-NEXT: ret i32 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i32 @load_i32_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <4 x i8> [[RET_SLICE_3]] to i32
; RELAXED_OOB_ONLY-NEXT: ret i32 [[RET]]
;
; BOTH_FLAGS-LABEL: define i32 @load_i32_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i32 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i32, ptr addrspace(7) %q, align 1
ret i32 %ret
}
define void @store_i32_align1(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align1(
; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <4 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i32_align1(
; UNALIGNED_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align1(
; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i32_align1(
; BOTH_FLAGS-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i32 %data, ptr addrspace(7) %q, align 1
ret void
}
define i64 @load_i64_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i64 @load_i64_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret i64 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i64 @load_i64_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i64 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i64 @load_i64_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret i64 [[RET]]
;
; BOTH_FLAGS-LABEL: define i64 @load_i64_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i64 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i64, ptr addrspace(7) %q, align 4
ret i64 %ret
}
define void @store_i64_align4(i64 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i64_align4(
; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i64_align4(
; UNALIGNED_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i64_align4(
; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i64_align4(
; BOTH_FLAGS-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i64 %data, ptr addrspace(7) %q, align 4
ret void
}
define i64 @load_i64_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i64 @load_i64_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to i64
; STRICT-NEXT: ret i64 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i64 @load_i64_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i64 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i64 @load_i64_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to i64
; RELAXED_OOB_ONLY-NEXT: ret i64 [[RET]]
;
; BOTH_FLAGS-LABEL: define i64 @load_i64_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i64 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i64, ptr addrspace(7) %q, align 1
ret i64 %ret
}
define void @store_i64_align1(i64 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i64_align1(
; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i64 [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i64_align1(
; UNALIGNED_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i64_align1(
; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i64 [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i64_align1(
; BOTH_FLAGS-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i64 %data, ptr addrspace(7) %q, align 1
ret void
}
define <2 x i32> @load_v2i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <2 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; STRICT-NEXT: ret <2 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i32> @load_v2i32_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i32> poison, i32 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i32> @load_v2i32_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i32>, ptr addrspace(7) %q, align 4
ret <2 x i32> %ret
}
define void @store_v2i32_align4(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align4(
; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i32> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i32_align4(
; UNALIGNED_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i32> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i32> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align4(
; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i32_align4(
; BOTH_FLAGS-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i32> %data, ptr addrspace(7) %q, align 4
ret void
}
define <2 x i32> @load_v2i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i16> [[RET_SLICE_1]], i16 [[RET_OFF_4]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i16> [[RET_SLICE_2]], i16 [[RET_OFF_6]], i64 3
; STRICT-NEXT: [[RET:%.*]] = bitcast <4 x i16> [[RET_SLICE_3]] to <2 x i32>
; STRICT-NEXT: ret <2 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i32> @load_v2i32_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i32> poison, i32 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i16> [[RET_SLICE_1]], i16 [[RET_OFF_4]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i16> [[RET_SLICE_2]], i16 [[RET_OFF_6]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <4 x i16> [[RET_SLICE_3]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i32> @load_v2i32_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i32>, ptr addrspace(7) %q, align 2
ret <2 x i32> %ret
}
define void @store_v2i32_align2(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align2(
; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <4 x i16>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_3]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i32_align2(
; UNALIGNED_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i32> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i32> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align2(
; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <4 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_3]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i32_align2(
; BOTH_FLAGS-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i32> %data, ptr addrspace(7) %q, align 2
ret void
}
define <2 x i32> @load_v2i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <2 x i32>
; STRICT-NEXT: ret <2 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i32> @load_v2i32_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i32> poison, i32 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i32> @load_v2i32_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i32>, ptr addrspace(7) %q, align 1
ret <2 x i32> %ret
}
define void @store_v2i32_align1(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align1(
; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i32_align1(
; UNALIGNED_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i32> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i32> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align1(
; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i32_align1(
; BOTH_FLAGS-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i32> %data, ptr addrspace(7) %q, align 1
ret void
}
define <3 x i32> @load_v3i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <3 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <3 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <3 x i32> [[RET_SLICE_1]], i32 [[RET_OFF_8]], i64 2
; STRICT-NEXT: ret <3 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <3 x i32> @load_v3i32_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <3 x i32> poison, i32 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <3 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <3 x i32> [[RET_SLICE_1]], i32 [[RET_OFF_8]], i64 2
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <3 x i32> @load_v3i32_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <3 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <3 x i32>, ptr addrspace(7) %q, align 4
ret <3 x i32> %ret
}
define void @store_v3i32_align4(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align4(
; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <3 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <3 x i32> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <3 x i32> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v3i32_align4(
; UNALIGNED_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <3 x i32> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <3 x i32> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <3 x i32> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align4(
; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v3i32_align4(
; BOTH_FLAGS-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <3 x i32> %data, ptr addrspace(7) %q, align 4
ret void
}
define <3 x i32> @load_v3i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align8(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i32> poison, <3 x i32> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <3 x i32> [[RET_PARTS_0]], i32 [[RET_OFF_8]], i64 2
; STRICT-NEXT: ret <3 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <3 x i32> @load_v3i32_align8(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i32> poison, <3 x i32> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <3 x i32> [[RET_PARTS_0]], i32 [[RET_OFF_8]], i64 2
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align8(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <3 x i32> @load_v3i32_align8(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <3 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <3 x i32>, ptr addrspace(7) %q, align 8
ret <3 x i32> %ret
}
define void @store_v3i32_align8(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align8(
; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i32> [[DATA]], <3 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <3 x i32> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v3i32_align8(
; UNALIGNED_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i32> [[DATA]], <3 x i32> poison, <2 x i32> <i32 0, i32 1>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <3 x i32> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align8(
; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v3i32_align8(
; BOTH_FLAGS-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <3 x i32> %data, ptr addrspace(7) %q, align 8
ret void
}
define <3 x i32> @load_v3i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align16(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret <3 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <3 x i32> @load_v3i32_align16(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align16(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <3 x i32> @load_v3i32_align16(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <3 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <3 x i32>, ptr addrspace(7) %q, align 16
ret <3 x i32> %ret
}
define void @store_v3i32_align16(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align16(
; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v3i32_align16(
; UNALIGNED_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align16(
; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v3i32_align16(
; BOTH_FLAGS-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <3 x i32> %data, ptr addrspace(7) %q, align 16
ret void
}
define <4 x i32> @load_v4i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i32> @load_v4i32_align8(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <4 x i32> poison, <4 x i32> [[RET_EXT_0]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; STRICT-NEXT: [[RET:%.*]] = shufflevector <4 x i32> [[RET_PARTS_0]], <4 x i32> [[RET_EXT_2]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; STRICT-NEXT: ret <4 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <4 x i32> @load_v4i32_align8(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <4 x i32> poison, <4 x i32> [[RET_EXT_0]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = shufflevector <4 x i32> [[RET_PARTS_0]], <4 x i32> [[RET_EXT_2]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; UNALIGNED_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i32> @load_v4i32_align8(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <4 x i32> @load_v4i32_align8(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <4 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <4 x i32>, ptr addrspace(7) %q, align 8
ret <4 x i32> %ret
}
define void @store_v4i32_align8(<4 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i32_align8(
; STRICT-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <4 x i32> [[DATA]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <4 x i32> [[DATA]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v4i32_align8(
; UNALIGNED_ONLY-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <4 x i32> [[DATA]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <4 x i32> [[DATA]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i32_align8(
; RELAXED_OOB_ONLY-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v4i32_align8(
; BOTH_FLAGS-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <4 x i32> %data, ptr addrspace(7) %q, align 8
ret void
}
define <8 x i32> @load_v8i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align16(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; STRICT-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; STRICT-NEXT: ret <8 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <8 x i32> @load_v8i32_align16(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align16(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; RELAXED_OOB_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <8 x i32> @load_v8i32_align16(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; BOTH_FLAGS-NEXT: ret <8 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <8 x i32>, ptr addrspace(7) %q, align 16
ret <8 x i32> %ret
}
define void @store_v8i32_align16(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align16(
; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v8i32_align16(
; UNALIGNED_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align16(
; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v8i32_align16(
; BOTH_FLAGS-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <8 x i32> %data, ptr addrspace(7) %q, align 16
ret void
}
define <8 x i32> @load_v8i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align8(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_2:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_2]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7>
; STRICT-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[RET_OFF_16:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_4:%.*]] = shufflevector <2 x i32> [[RET_OFF_16]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <8 x i32> [[RET_PARTS_2]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7>
; STRICT-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[RET_OFF_24:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_6:%.*]] = shufflevector <2 x i32> [[RET_OFF_24]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_4]], <8 x i32> [[RET_EXT_6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; STRICT-NEXT: ret <8 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <8 x i32> @load_v8i32_align8(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_2:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_2]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <2 x i32> [[RET_OFF_16]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <8 x i32> [[RET_PARTS_2]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[RET_OFF_24:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_6:%.*]] = shufflevector <2 x i32> [[RET_OFF_24]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_4]], <8 x i32> [[RET_EXT_6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align8(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; RELAXED_OOB_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <8 x i32> @load_v8i32_align8(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; BOTH_FLAGS-NEXT: ret <8 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <8 x i32>, ptr addrspace(7) %q, align 8
ret <8 x i32> %ret
}
define void @store_v8i32_align8(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align8(
; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_6]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v8i32_align8(
; UNALIGNED_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_6]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align8(
; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v8i32_align8(
; BOTH_FLAGS-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <8 x i32> %data, ptr addrspace(7) %q, align 8
ret void
}
define <8 x i32> @load_v8i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i32> [[RET_SLICE_1]], i32 [[RET_OFF_8]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_12:%.*]] = add i32 [[Q]], 12
; STRICT-NEXT: [[RET_OFF_12:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_12]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i32> [[RET_SLICE_2]], i32 [[RET_OFF_12]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[RET_OFF_16:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i32> [[RET_SLICE_3]], i32 [[RET_OFF_16]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_20:%.*]] = add i32 [[Q]], 20
; STRICT-NEXT: [[RET_OFF_20:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_20]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i32> [[RET_SLICE_4]], i32 [[RET_OFF_20]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[RET_OFF_24:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i32> [[RET_SLICE_5]], i32 [[RET_OFF_24]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_28:%.*]] = add i32 [[Q]], 28
; STRICT-NEXT: [[RET_OFF_28:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_28]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <8 x i32> [[RET_SLICE_6]], i32 [[RET_OFF_28]], i64 7
; STRICT-NEXT: ret <8 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <8 x i32> @load_v8i32_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i32> poison, i32 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i32> [[RET_SLICE_0]], i32 [[RET_OFF_4]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i32> [[RET_SLICE_1]], i32 [[RET_OFF_8]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_12:%.*]] = add i32 [[Q]], 12
; UNALIGNED_ONLY-NEXT: [[RET_OFF_12:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_12]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i32> [[RET_SLICE_2]], i32 [[RET_OFF_12]], i64 3
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[RET_OFF_16:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i32> [[RET_SLICE_3]], i32 [[RET_OFF_16]], i64 4
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_20:%.*]] = add i32 [[Q]], 20
; UNALIGNED_ONLY-NEXT: [[RET_OFF_20:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_20]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i32> [[RET_SLICE_4]], i32 [[RET_OFF_20]], i64 5
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[RET_OFF_24:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i32> [[RET_SLICE_5]], i32 [[RET_OFF_24]], i64 6
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_28:%.*]] = add i32 [[Q]], 28
; UNALIGNED_ONLY-NEXT: [[RET_OFF_28:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_28]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <8 x i32> [[RET_SLICE_6]], i32 [[RET_OFF_28]], i64 7
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; RELAXED_OOB_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <8 x i32> @load_v8i32_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET:%.*]] = shufflevector <8 x i32> [[RET_PARTS_0]], <8 x i32> [[RET_EXT_4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; BOTH_FLAGS-NEXT: ret <8 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <8 x i32>, ptr addrspace(7) %q, align 4
ret <8 x i32> %ret
}
define void @store_v8i32_align4(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align4(
; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i32> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i32> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 12
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i32> [[DATA]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_3]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i32> [[DATA]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 20
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i32> [[DATA]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_5]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i32> [[DATA]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_6]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 28
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i32> [[DATA]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_7]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v8i32_align4(
; UNALIGNED_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i32> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i32> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_1]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i32> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_2]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 12
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i32> [[DATA]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_3]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i32> [[DATA]], i64 4
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 20
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i32> [[DATA]], i64 5
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_5]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i32> [[DATA]], i64 6
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_6]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 28
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i32> [[DATA]], i64 7
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_7]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align4(
; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v8i32_align4(
; BOTH_FLAGS-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <8 x i32> %data, ptr addrspace(7) %q, align 4
ret void
}
define <10 x i32> @load_v10i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <10 x i32> @load_v10i32_align16(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_32:%.*]] = add i32 [[Q]], 32
; STRICT-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; STRICT-NEXT: ret <10 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <10 x i32> @load_v10i32_align16(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_32:%.*]] = add i32 [[Q]], 32
; UNALIGNED_ONLY-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; UNALIGNED_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <10 x i32> @load_v10i32_align16(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_32:%.*]] = add nuw i32 [[Q]], 32
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; RELAXED_OOB_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <10 x i32> @load_v10i32_align16(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_32:%.*]] = add nuw i32 [[Q]], 32
; BOTH_FLAGS-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; BOTH_FLAGS-NEXT: ret <10 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <10 x i32>, ptr addrspace(7) %q, align 16
ret <10 x i32> %ret
}
define void @store_v10i32_align16(<10 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v10i32_align16(
; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_8:%.*]] = add i32 [[Q]], 32
; STRICT-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v10i32_align16(
; UNALIGNED_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_8:%.*]] = add i32 [[Q]], 32
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v10i32_align16(
; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_8:%.*]] = add nuw i32 [[Q]], 32
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v10i32_align16(
; BOTH_FLAGS-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_8:%.*]] = add nuw i32 [[Q]], 32
; BOTH_FLAGS-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <10 x i32> %data, ptr addrspace(7) %q, align 16
ret void
}
define <10 x i32> @load_v10i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <10 x i32> @load_v10i32_align8(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_2:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_2]], <10 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[RET_OFF_16:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_4:%.*]] = shufflevector <2 x i32> [[RET_OFF_16]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_2]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[RET_OFF_24:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_6:%.*]] = shufflevector <2 x i32> [[RET_OFF_24]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_6:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_6]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 10, i32 11, i32 8, i32 9>
; STRICT-NEXT: [[Q_OFF_PTR_32:%.*]] = add i32 [[Q]], 32
; STRICT-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_6]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; STRICT-NEXT: ret <10 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <10 x i32> @load_v10i32_align8(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[RET_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_2:%.*]] = shufflevector <2 x i32> [[RET_OFF_8]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_2:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_2]], <10 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <2 x i32> [[RET_OFF_16]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_2]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_24:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[RET_OFF_24:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_24]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_6:%.*]] = shufflevector <2 x i32> [[RET_OFF_24]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET_PARTS_6:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_6]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 10, i32 11, i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_32:%.*]] = add i32 [[Q]], 32
; UNALIGNED_ONLY-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_6]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; UNALIGNED_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <10 x i32> @load_v10i32_align8(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_32:%.*]] = add nuw i32 [[Q]], 32
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; RELAXED_OOB_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <10 x i32> @load_v10i32_align8(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_16:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[RET_OFF_16:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_16]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_4:%.*]] = shufflevector <4 x i32> [[RET_OFF_16]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET_PARTS_4:%.*]] = shufflevector <10 x i32> [[RET_PARTS_0]], <10 x i32> [[RET_EXT_4]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 11, i32 12, i32 13, i32 8, i32 9>
; BOTH_FLAGS-NEXT: [[Q_OFF_PTR_32:%.*]] = add nuw i32 [[Q]], 32
; BOTH_FLAGS-NEXT: [[RET_OFF_32:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q_OFF_PTR_32]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET_EXT_8:%.*]] = shufflevector <2 x i32> [[RET_OFF_32]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BOTH_FLAGS-NEXT: [[RET:%.*]] = shufflevector <10 x i32> [[RET_PARTS_4]], <10 x i32> [[RET_EXT_8]], <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 10, i32 11>
; BOTH_FLAGS-NEXT: ret <10 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <10 x i32>, ptr addrspace(7) %q, align 8
ret <10 x i32> %ret
}
define void @store_v10i32_align8(<10 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v10i32_align8(
; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 4, i32 5>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 6, i32 7>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_6]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_8:%.*]] = add i32 [[Q]], 32
; STRICT-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v10i32_align8(
; UNALIGNED_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 0, i32 1>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 2, i32 3>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_2]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 4, i32 5>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 24
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 6, i32 7>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_6]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_8:%.*]] = add i32 [[Q]], 32
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v10i32_align8(
; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_8:%.*]] = add nuw i32 [[Q]], 32
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v10i32_align8(
; BOTH_FLAGS-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
; BOTH_FLAGS-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_4]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[Q_PART_8:%.*]] = add nuw i32 [[Q]], 32
; BOTH_FLAGS-NEXT: [[DATA_SLICE_8:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 8, i32 9>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_8]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q_PART_8]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <10 x i32> %data, ptr addrspace(7) %q, align 8
ret void
}
define i16 @load_i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i16 @load_i16_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[RET:%.*]] = bitcast <2 x i8> [[RET_SLICE_1]] to i16
; STRICT-NEXT: ret i16 [[RET]]
;
; UNALIGNED_ONLY-LABEL: define i16 @load_i16_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret i16 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i16 @load_i16_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i8> [[RET_SLICE_1]] to i16
; RELAXED_OOB_ONLY-NEXT: ret i16 [[RET]]
;
; BOTH_FLAGS-LABEL: define i16 @load_i16_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret i16 [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load i16, ptr addrspace(7) %q, align 1
ret i16 %ret
}
define void @store_i16_align1(i16 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i16_align1(
; STRICT-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i16 [[DATA]] to <2 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_i16_align1(
; UNALIGNED_ONLY-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i16_align1(
; RELAXED_OOB_ONLY-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i16 [[DATA]] to <2 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_i16_align1(
; BOTH_FLAGS-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store i16 %data, ptr addrspace(7) %q, align 1
ret void
}
define <2 x i16> @load_v2i16_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; STRICT-NEXT: ret <2 x i16> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i16> @load_v2i16_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i16> @load_v2i16_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i16> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i16>, ptr addrspace(7) %q, align 4
ret <2 x i16> %ret
}
define void @store_v2i16_align4(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align4(
; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i16_align4(
; UNALIGNED_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align4(
; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i16_align4(
; BOTH_FLAGS-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i16> %data, ptr addrspace(7) %q, align 4
ret void
}
define <2 x i16> @load_v2i16_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; STRICT-NEXT: ret <2 x i16> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i16> @load_v2i16_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i16> @load_v2i16_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i16> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i16>, ptr addrspace(7) %q, align 2
ret <2 x i16> %ret
}
define void @store_v2i16_align2(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align2(
; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i16_align2(
; UNALIGNED_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align2(
; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i16_align2(
; BOTH_FLAGS-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i16> %data, ptr addrspace(7) %q, align 2
ret void
}
define <2 x i16> @load_v2i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[RET:%.*]] = bitcast <4 x i8> [[RET_SLICE_3]] to <2 x i16>
; STRICT-NEXT: ret <2 x i16> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i16> @load_v2i16_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <4 x i8> [[RET_SLICE_3]] to <2 x i16>
; RELAXED_OOB_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i16> @load_v2i16_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <2 x i16> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i16>, ptr addrspace(7) %q, align 1
ret <2 x i16> %ret
}
define void @store_v2i16_align1(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align1(
; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i16> [[DATA]] to <4 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i16_align1(
; UNALIGNED_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align1(
; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i16> [[DATA]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i16_align1(
; BOTH_FLAGS-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i16> %data, ptr addrspace(7) %q, align 1
ret void
}
define <2 x i8> @load_v2i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i8> @load_v2i8_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: ret <2 x i8> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i8> @load_v2i8_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i8> @load_v2i8_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <2 x i8>
; RELAXED_OOB_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i8> @load_v2i8_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <2 x i8>
; BOTH_FLAGS-NEXT: ret <2 x i8> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i8>, ptr addrspace(7) %q, align 2
ret <2 x i8> %ret
}
define void @store_v2i8_align2(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i8_align2(
; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i8_align2(
; UNALIGNED_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i8_align2(
; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i8> [[DATA]] to i16
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i8_align2(
; BOTH_FLAGS-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i8> [[DATA]] to i16
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i8> %data, ptr addrspace(7) %q, align 2
ret void
}
define <2 x i8> @load_v2i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i8> @load_v2i8_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: ret <2 x i8> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <2 x i8> @load_v2i8_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i8> @load_v2i8_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = insertelement <2 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; BOTH_FLAGS-LABEL: define <2 x i8> @load_v2i8_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <2 x i8>
; BOTH_FLAGS-NEXT: ret <2 x i8> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <2 x i8>, ptr addrspace(7) %q, align 1
ret <2 x i8> %ret
}
define void @store_v2i8_align1(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i8_align1(
; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v2i8_align1(
; UNALIGNED_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i8_align1(
; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i8> [[DATA]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v2i8_align1(
; BOTH_FLAGS-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i8> [[DATA]] to i16
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <2 x i8> %data, ptr addrspace(7) %q, align 1
ret void
}
define <4 x i8> @load_v4i8_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: ret <4 x i8> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <4 x i8> @load_v4i8_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; BOTH_FLAGS-LABEL: define <4 x i8> @load_v4i8_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; BOTH_FLAGS-NEXT: ret <4 x i8> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <4 x i8>, ptr addrspace(7) %q, align 4
ret <4 x i8> %ret
}
define void @store_v4i8_align4(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align4(
; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v4i8_align4(
; UNALIGNED_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align4(
; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v4i8_align4(
; BOTH_FLAGS-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <4 x i8> %data, ptr addrspace(7) %q, align 4
ret void
}
define <4 x i8> @load_v4i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: ret <4 x i8> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <4 x i8> @load_v4i8_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <2 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i16> [[RET_SLICE_1]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; BOTH_FLAGS-LABEL: define <4 x i8> @load_v4i8_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; BOTH_FLAGS-NEXT: ret <4 x i8> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <4 x i8>, ptr addrspace(7) %q, align 2
ret <4 x i8> %ret
}
define void @store_v4i8_align2(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align2(
; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v4i8_align2(
; UNALIGNED_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align2(
; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to <2 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v4i8_align2(
; BOTH_FLAGS-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <4 x i8> %data, ptr addrspace(7) %q, align 2
ret void
}
define <4 x i8> @load_v4i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: ret <4 x i8> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <4 x i8> @load_v4i8_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = insertelement <4 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; BOTH_FLAGS-LABEL: define <4 x i8> @load_v4i8_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; BOTH_FLAGS-NEXT: ret <4 x i8> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <4 x i8>, ptr addrspace(7) %q, align 1
ret <4 x i8> %ret
}
define void @store_v4i8_align1(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align1(
; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v4i8_align1(
; UNALIGNED_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align1(
; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i8> [[DATA]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i8> [[DATA]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i8> [[DATA]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v4i8_align1(
; BOTH_FLAGS-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <4 x i8> %data, ptr addrspace(7) %q, align 1
ret void
}
define <16 x i4> @load_v16i4_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align8(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; STRICT-NEXT: ret <16 x i4> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <16 x i4> @load_v16i4_align8(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align8(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; BOTH_FLAGS-LABEL: define <16 x i4> @load_v16i4_align8(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; BOTH_FLAGS-NEXT: ret <16 x i4> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <16 x i4>, ptr addrspace(7) %q, align 8
ret <16 x i4> %ret
}
define void @store_v16i4_align8(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align8(
; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v16i4_align8(
; UNALIGNED_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align8(
; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v16i4_align8(
; BOTH_FLAGS-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <16 x i4> %data, ptr addrspace(7) %q, align 8
ret void
}
define <16 x i4> @load_v16i4_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align4(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; STRICT-NEXT: ret <16 x i4> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <16 x i4> @load_v16i4_align4(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align4(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; BOTH_FLAGS-LABEL: define <16 x i4> @load_v16i4_align4(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; BOTH_FLAGS-NEXT: ret <16 x i4> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <16 x i4>, ptr addrspace(7) %q, align 4
ret <16 x i4> %ret
}
define void @store_v16i4_align4(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align4(
; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v16i4_align4(
; UNALIGNED_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align4(
; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v16i4_align4(
; BOTH_FLAGS-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <16 x i4> %data, ptr addrspace(7) %q, align 4
ret void
}
define <16 x i4> @load_v16i4_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align2(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; STRICT-NEXT: ret <16 x i4> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <16 x i4> @load_v16i4_align2(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align2(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <4 x i16> [[RET_SLICE_0]], i16 [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <4 x i16> [[RET_SLICE_1]], i16 [[RET_OFF_4]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <4 x i16> [[RET_SLICE_2]], i16 [[RET_OFF_6]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <4 x i16> [[RET_SLICE_3]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; BOTH_FLAGS-LABEL: define <16 x i4> @load_v16i4_align2(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; BOTH_FLAGS-NEXT: ret <16 x i4> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <16 x i4>, ptr addrspace(7) %q, align 2
ret <16 x i4> %ret
}
define void @store_v16i4_align2(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align2(
; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v16i4_align2(
; UNALIGNED_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align2(
; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <4 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_1]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_2]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_3]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v16i4_align2(
; BOTH_FLAGS-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <16 x i4> %data, ptr addrspace(7) %q, align 2
ret void
}
define <16 x i4> @load_v16i4_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align1(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; STRICT-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; STRICT-NEXT: ret <16 x i4> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <16 x i4> @load_v16i4_align1(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; UNALIGNED_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align1(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x i8> [[RET_SLICE_0]], i8 [[RET_OFF_1]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x i8> [[RET_SLICE_1]], i8 [[RET_OFF_2]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_3:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x i8> [[RET_SLICE_2]], i8 [[RET_OFF_3]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x i8> [[RET_SLICE_3]], i8 [[RET_OFF_4]], i64 4
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_5:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x i8> [[RET_SLICE_4]], i8 [[RET_OFF_5]], i64 5
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x i8> [[RET_SLICE_5]], i8 [[RET_OFF_6]], i64 6
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_7:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q_OFF_PTR_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_7:%.*]] = insertelement <8 x i8> [[RET_SLICE_6]], i8 [[RET_OFF_7]], i64 7
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <8 x i8> [[RET_SLICE_7]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; BOTH_FLAGS-LABEL: define <16 x i4> @load_v16i4_align1(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; BOTH_FLAGS-NEXT: ret <16 x i4> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
%ret = load <16 x i4>, ptr addrspace(7) %q, align 1
ret <16 x i4> %ret
}
define void @store_v16i4_align1(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align1(
; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; STRICT-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; STRICT-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; STRICT-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; STRICT-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
; UNALIGNED_ONLY-LABEL: define void @store_v16i4_align1(
; UNALIGNED_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 2
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_3:%.*]] = add i32 [[Q]], 3
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 4
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_5:%.*]] = add i32 [[Q]], 5
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_6:%.*]] = add i32 [[Q]], 6
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: [[Q_PART_7:%.*]] = add i32 [[Q]], 7
; UNALIGNED_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; UNALIGNED_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align1(
; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 1
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_1]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_1]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 2
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_2]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_3:%.*]] = add nuw i32 [[Q]], 3
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_3:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 3
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_3]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_3]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 4
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_4]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_5:%.*]] = add nuw i32 [[Q]], 5
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_5:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 5
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_5]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_5]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_6:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 6
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_6]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_7:%.*]] = add nuw i32 [[Q]], 7
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_7:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 7
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_7]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q_PART_7]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
; BOTH_FLAGS-LABEL: define void @store_v16i4_align1(
; BOTH_FLAGS-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; BOTH_FLAGS-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret void
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off
store <16 x i4> %data, ptr addrspace(7) %q, align 1
ret void
}
define <4 x i32> @load_v4i32_align8_nneg(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; STRICT-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret <4 x i32> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
; UNALIGNED_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; BOTH_FLAGS-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
; BOTH_FLAGS-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <4 x i32> [[RET]]
;
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%off.clamped = call i32 @llvm.umin.i32(i32 %off, i32 2147483640)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off.clamped
%ret = load <4 x i32>, ptr addrspace(7) %q, align 8
ret <4 x i32> %ret
}
define <8 x half> @load_v8f16_align2_not_oob(ptr addrspace(1) inreg %ptr, i32 %off) {
; STRICT-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
; STRICT-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; STRICT-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; STRICT-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x half> poison, half [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
; STRICT-NEXT: [[RET_OFF_2:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x half> [[RET_SLICE_0]], half [[RET_OFF_2]], i64 1
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
; STRICT-NEXT: [[RET_OFF_4:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x half> [[RET_SLICE_1]], half [[RET_OFF_4]], i64 2
; STRICT-NEXT: [[Q_OFF_PTR_6:%.*]] = add i32 [[Q]], 6
; STRICT-NEXT: [[RET_OFF_6:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x half> [[RET_SLICE_2]], half [[RET_OFF_6]], i64 3
; STRICT-NEXT: [[Q_OFF_PTR_8:%.*]] = add i32 [[Q]], 8
; STRICT-NEXT: [[RET_OFF_8:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x half> [[RET_SLICE_3]], half [[RET_OFF_8]], i64 4
; STRICT-NEXT: [[Q_OFF_PTR_10:%.*]] = add i32 [[Q]], 10
; STRICT-NEXT: [[RET_OFF_10:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_10]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x half> [[RET_SLICE_4]], half [[RET_OFF_10]], i64 5
; STRICT-NEXT: [[Q_OFF_PTR_12:%.*]] = add i32 [[Q]], 12
; STRICT-NEXT: [[RET_OFF_12:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_12]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x half> [[RET_SLICE_5]], half [[RET_OFF_12]], i64 6
; STRICT-NEXT: [[Q_OFF_PTR_14:%.*]] = add i32 [[Q]], 14
; STRICT-NEXT: [[RET_OFF_14:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_14]], i32 0, i32 0)
; STRICT-NEXT: [[RET:%.*]] = insertelement <8 x half> [[RET_SLICE_6]], half [[RET_OFF_14]], i64 7
; STRICT-NEXT: ret <8 x half> [[RET]]
;
; UNALIGNED_ONLY-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
; UNALIGNED_ONLY-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; UNALIGNED_ONLY-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; UNALIGNED_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; UNALIGNED_ONLY-NEXT: [[RET:%.*]] = call <8 x half> @llvm.amdgcn.raw.ptr.buffer.load.v8f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; UNALIGNED_ONLY-NEXT: ret <8 x half> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
; RELAXED_OOB_ONLY-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; RELAXED_OOB_ONLY-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; RELAXED_OOB_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x half> poison, half [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_2:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_2]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_1:%.*]] = insertelement <8 x half> [[RET_SLICE_0]], half [[RET_OFF_2]], i64 1
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_4:%.*]] = add nuw i32 [[Q]], 4
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_4:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_4]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_2:%.*]] = insertelement <8 x half> [[RET_SLICE_1]], half [[RET_OFF_4]], i64 2
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_6:%.*]] = add nuw i32 [[Q]], 6
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_6:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_6]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_3:%.*]] = insertelement <8 x half> [[RET_SLICE_2]], half [[RET_OFF_6]], i64 3
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_8:%.*]] = add nuw i32 [[Q]], 8
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_8:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_8]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_4:%.*]] = insertelement <8 x half> [[RET_SLICE_3]], half [[RET_OFF_8]], i64 4
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_10:%.*]] = add nuw i32 [[Q]], 10
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_10:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_10]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_5:%.*]] = insertelement <8 x half> [[RET_SLICE_4]], half [[RET_OFF_10]], i64 5
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_12:%.*]] = add nuw i32 [[Q]], 12
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_12:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_12]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_6:%.*]] = insertelement <8 x half> [[RET_SLICE_5]], half [[RET_OFF_12]], i64 6
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_14:%.*]] = add nuw i32 [[Q]], 14
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_14:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q_OFF_PTR_14]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = insertelement <8 x half> [[RET_SLICE_6]], half [[RET_OFF_14]], i64 7
; RELAXED_OOB_ONLY-NEXT: ret <8 x half> [[RET]]
;
; BOTH_FLAGS-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
; BOTH_FLAGS-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
; BOTH_FLAGS-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; BOTH_FLAGS-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; BOTH_FLAGS-NEXT: [[RET:%.*]] = call <8 x half> @llvm.amdgcn.raw.ptr.buffer.load.v8f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; BOTH_FLAGS-NEXT: ret <8 x half> [[RET]]
;
%buf = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) %ptr, i16 0, i64 8192, i32 159744)
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
%off.clamped = call i32 @llvm.umin.i32(i32 %off, i32 1024)
%q = getelementptr i8, ptr addrspace(7) %p, i32 %off.clamped
%ret = load <8 x half>, ptr addrspace(7) %q, align 2
ret <8 x half> %ret
}
!llvm.module.flags = !{!0}
!0 = !{i32 7, !"amdgpu.buffer.oob.mode", i32 BUFFER_OOB_MODE}