llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.indexed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu13.10 -mattr=+real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GCN-TRUE16 %s
; RUN: llc -mtriple=amdgpu13.10 -mattr=-real-true16 -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GCN-FAKE16 %s

define amdgpu_ps <4 x float> @load_2dmsaa(i32 inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
; GCN-NEXT:    v_mov_b32_e32 v6, v0 ; encoding: [0x00,0x03,0x0c,0x7e]
; GCN-NEXT:    image_msaa_load v[0:3], [v6, v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x06,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x06,0x05,0x04,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2dmsaa_both(i32 inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_both:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v8, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x08,0x07]
; GCN-NEXT:    v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x06,0x05]
; GCN-NEXT:    s_mov_b32 s3, s2 ; encoding: [0x02,0x03,0x83,0xbe]
; GCN-NEXT:    s_mov_b32 s2, s1 ; encoding: [0x01,0x03,0x82,0xbe]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; encoding: [0x22,0x01,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8 ; encoding: [0x08,0x01,0x10,0xca,0x08,0x01,0x0a,0x09]
; GCN-NEXT:    v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8 ; encoding: [0x08,0x01,0x10,0xca,0x08,0x01,0x0c,0x0b]
; GCN-NEXT:    v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 ; encoding: [0x08,0x01,0x10,0xca,0x09,0x01,0x00,0x00]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x92,0x01,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; encoding: [0x0a,0x01,0x10,0xca,0x0b,0x01,0x02,0x02]
; GCN-NEXT:    v_mov_b32_e32 v4, v12 ; encoding: [0x0c,0x03,0x08,0x7e]
; GCN-NEXT:    image_msaa_load v[0:4], [v7, v6, v5], rsrcidx(s0) dmask:0x2 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ; encoding: [0x0e,0x20,0xa0,0xe4,0x00,0x01,0x01,0x00,0x07,0x06,0x05,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    global_store_b32 v8, v4, s[2:3] ; encoding: [0x02,0x00,0x07,0xee,0x00,0x00,0x00,0x02,0x08,0x00,0x00,0x00]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call {<4 x float>,i32} @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32i32.i32(i32 2, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 3, i32 0)
  %v.vec = extractvalue {<4 x float>, i32} %v, 0
  %v.err = extractvalue {<4 x float>, i32} %v, 1
  store i32 %v.err, ptr addrspace(1) %out, align 4
  ret <4 x float> %v.vec
}

define amdgpu_ps <4 x float> @load_2darraymsaa(i32 inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GCN-LABEL: load_2darraymsaa:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v5, v2 ; encoding: [0x03,0x01,0x10,0xca,0x02,0x01,0x04,0x04]
; GCN-NEXT:    v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v0 ; encoding: [0x01,0x01,0x10,0xca,0x00,0x01,0x06,0x06]
; GCN-NEXT:    image_msaa_load v[0:3], [v7, v6, v5, v4], rsrcidx(s0) dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x07,0x20,0x20,0xe5,0x00,0x00,0x01,0x00,0x07,0x06,0x05,0x04]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i32(i32 4, i32 %s, i32 %t, i32 %slice, i32 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(i32 inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GCN-LABEL: load_2darraymsaa_tfe:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v5, v3 ; encoding: [0x80,0x80,0x20,0xcf,0x03,0x01,0x00,0x00,0x09,0x00,0x00,0x05]
; GCN-NEXT:    v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x06,0x06]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; encoding: [0xb2,0x01,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v10, v9 ; encoding: [0x00,0x81,0x20,0xcf,0x09,0x01,0x00,0x00,0x08,0x00,0x00,0x0a]
; GCN-NEXT:    v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, v9 ; encoding: [0x09,0x01,0x10,0xca,0x09,0x01,0x0c,0x0b]
; GCN-NEXT:    v_mov_b32_e32 v13, v9 ; encoding: [0x09,0x03,0x1a,0x7e]
; GCN-NEXT:    v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 ; encoding: [0x09,0x01,0x10,0xca,0x0a,0x01,0x00,0x00]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; encoding: [0x93,0x01,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; encoding: [0x0b,0x01,0x10,0xca,0x0c,0x01,0x02,0x02]
; GCN-NEXT:    v_mov_b32_e32 v4, v13 ; encoding: [0x0d,0x03,0x08,0x7e]
; GCN-NEXT:    image_msaa_load v[0:4], [v8, v7, v6, v5], rsrcidx(s0) dmask:0x8 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; encoding: [0x0f,0x20,0x20,0xe6,0x00,0x00,0x01,0x00,0x08,0x07,0x06,0x05]
; GCN-NEXT:    s_mov_b32 s3, s2 ; encoding: [0x02,0x03,0x83,0xbe]
; GCN-NEXT:    s_mov_b32 s2, s1 ; encoding: [0x01,0x03,0x82,0xbe]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    global_store_b32 v9, v4, s[2:3] ; encoding: [0x02,0x00,0x07,0xee,0x00,0x00,0x00,0x02,0x09,0x00,0x00,0x00]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call {<4 x float>,i32} @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32i32.i32(i32 8, i32 %s, i32 %t, i32 %slice, i32 %fragid, i32 %rsrc, i32 1, i32 0)
  %v.vec = extractvalue {<4 x float>, i32} %v, 0
  %v.err = extractvalue {<4 x float>, i32} %v, 1
  store i32 %v.err, ptr addrspace(1) %out, align 4
  ret <4 x float> %v.vec
}

define amdgpu_ps <4 x float> @load_2dmsaa_glc(i32 inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_glc:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
; GCN-NEXT:    v_mov_b32_e32 v6, v0 ; encoding: [0x00,0x03,0x0c,0x7e]
; GCN-NEXT:    image_msaa_load v[0:3], [v6, v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_NT ; encoding: [0x06,0x20,0x60,0xe4,0x00,0x00,0x11,0x00,0x06,0x05,0x04,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 0, i32 1)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2dmsaa_slc(i32 inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_slc:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
; GCN-NEXT:    v_mov_b32_e32 v6, v0 ; encoding: [0x00,0x03,0x0c,0x7e]
; GCN-NEXT:    image_msaa_load v[0:3], [v6, v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_HT ; encoding: [0x06,0x20,0x60,0xe4,0x00,0x00,0x21,0x00,0x06,0x05,0x04,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 0, i32 2)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2dmsaa_glc_slc(i32 inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_glc_slc:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
; GCN-NEXT:    v_mov_b32_e32 v6, v0 ; encoding: [0x00,0x03,0x0c,0x7e]
; GCN-NEXT:    image_msaa_load v[0:3], [v6, v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm th:TH_LOAD_LU ; encoding: [0x06,0x20,0x60,0xe4,0x00,0x00,0x31,0x00,0x06,0x05,0x04,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 0, i32 3)
  ret <4 x float> %v
}

define amdgpu_ps <4 x half> @load_2dmsaa_d16(i32 inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_d16:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v0 ; encoding: [0x01,0x01,0x10,0xca,0x00,0x01,0x04,0x03]
; GCN-NEXT:    image_msaa_load v[0:1], [v4, v3, v2], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm d16 ; encoding: [0x26,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x04,0x03,0x02,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x half> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f16.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x half> %v
}

define amdgpu_ps <4 x half> @load_2dmsaa_tfe_d16(i32 inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %fragid) {
; GCN-LABEL: load_2dmsaa_tfe_d16:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x05]
; GCN-NEXT:    v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x03]
; GCN-NEXT:    s_mov_b32 s3, s2 ; encoding: [0x02,0x03,0x83,0xbe]
; GCN-NEXT:    s_mov_b32 s2, s1 ; encoding: [0x01,0x03,0x82,0xbe]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x92,0x00,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v6 ; encoding: [0x06,0x01,0x10,0xca,0x06,0x01,0x08,0x07]
; GCN-NEXT:    v_dual_mov_b32 v0, v6 :: v_dual_mov_b32 v1, v7 ; encoding: [0x06,0x01,0x10,0xca,0x07,0x01,0x00,0x00]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0xae,0xbf]
; GCN-NEXT:    v_mov_b32_e32 v2, v8 ; encoding: [0x08,0x03,0x04,0x7e]
; GCN-NEXT:    image_msaa_load v[0:2], [v5, v4, v3], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm tfe d16 ; encoding: [0x2e,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x05,0x04,0x03,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    global_store_b32 v6, v2, s[2:3] ; encoding: [0x02,0x00,0x07,0xee,0x00,0x00,0x00,0x01,0x06,0x00,0x00,0x00]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call {<4 x half>,i32} @llvm.amdgcn.image.msaa.load.2dmsaa.v4f16i32.i32(i32 1, i32 %s, i32 %t, i32 %fragid, i32 %rsrc, i32 1, i32 0)
  %v.vec = extractvalue {<4 x half>, i32} %v, 0
  %v.err = extractvalue {<4 x half>, i32} %v, 1
  store i32 %v.err, ptr addrspace(1) %out, align 4
  ret <4 x half> %v.vec
}

define amdgpu_ps <4 x half> @load_2darraymsaa_d16(i32 inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GCN-LABEL: load_2darraymsaa_d16:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0 ; encoding: [0x01,0x01,0x10,0xca,0x00,0x01,0x04,0x04]
; GCN-NEXT:    image_msaa_load v[0:1], [v5, v4, v2, v3], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm d16 ; encoding: [0x27,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x05,0x04,0x02,0x03]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x half> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f16.i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x half> %v
}

define amdgpu_ps <4 x half> @load_2darraymsaa_tfe_d16(i32 inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GCN-LABEL: load_2darraymsaa_tfe_d16:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, 0 ; encoding: [0x00,0x01,0x10,0xca,0x80,0x00,0x06,0x06]
; GCN-NEXT:    v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v5, v1 ; encoding: [0x02,0x01,0x10,0xca,0x01,0x01,0x04,0x04]
; GCN-NEXT:    s_mov_b32 s3, s2 ; encoding: [0x02,0x03,0x83,0xbe]
; GCN-NEXT:    s_mov_b32 s2, s1 ; encoding: [0x01,0x03,0x82,0xbe]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; encoding: [0x92,0x00,0xae,0xbf]
; GCN-NEXT:    v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; encoding: [0x07,0x01,0x10,0xca,0x07,0x01,0x08,0x08]
; GCN-NEXT:    v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 ; encoding: [0x07,0x01,0x10,0xca,0x08,0x01,0x00,0x00]
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_2) ; encoding: [0x02,0x00,0xae,0xbf]
; GCN-NEXT:    v_mov_b32_e32 v2, v9 ; encoding: [0x09,0x03,0x04,0x7e]
; GCN-NEXT:    image_msaa_load v[0:2], [v6, v5, v4, v3], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe d16 ; encoding: [0x2f,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x06,0x05,0x04,0x03]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    global_store_b32 v7, v2, s[2:3] ; encoding: [0x02,0x00,0x07,0xee,0x00,0x00,0x00,0x01,0x07,0x00,0x00,0x00]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call {<4 x half>,i32} @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f16i32.i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 %fragid, i32 %rsrc, i32 1, i32 0)
  %v.vec = extractvalue {<4 x half>, i32} %v, 0
  %v.err = extractvalue {<4 x half>, i32} %v, 1
  store i32 %v.err, ptr addrspace(1) %out, align 4
  ret <4 x half> %v.vec
}

define amdgpu_ps <4 x float> @load_2dmsaa_a16(i32 inreg %rsrc, i16 %s, i16 %t, i16 %fragid) {
; GCN-TRUE16-LABEL: load_2dmsaa_a16:
; GCN-TRUE16:       ; %bb.0: ; %main_body
; GCN-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v2.l ; encoding: [0x02,0x39,0x08,0x7e]
; GCN-TRUE16-NEXT:    v_perm_b32 v5, v1, v0, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
; GCN-TRUE16-NEXT:    image_msaa_load v[0:3], [v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x05,0x04,0x00,0x00]
; GCN-TRUE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-TRUE16-NEXT:    ; return to shader part epilog
;
; GCN-FAKE16-LABEL: load_2dmsaa_a16:
; GCN-FAKE16:       ; %bb.0: ; %main_body
; GCN-FAKE16-NEXT:    v_mov_b32_e32 v4, v2 ; encoding: [0x02,0x03,0x08,0x7e]
; GCN-FAKE16-NEXT:    v_perm_b32 v5, v1, v0, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
; GCN-FAKE16-NEXT:    image_msaa_load v[0:3], [v5, v4], rsrcidx(s0) dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x46,0x20,0x60,0xe4,0x00,0x00,0x01,0x00,0x05,0x04,0x00,0x00]
; GCN-FAKE16-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-FAKE16-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i16(i32 1, i16 %s, i16 %t, i16 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}

define amdgpu_ps <4 x float> @load_2darraymsaa_a16(i32 inreg %rsrc, i16 %s, i16 %t, i16 %slice, i16 %fragid) {
; GCN-LABEL: load_2darraymsaa_a16:
; GCN:       ; %bb.0: ; %main_body
; GCN-NEXT:    v_perm_b32 v4, v3, v2, 0x5040100 ; encoding: [0x04,0x00,0x44,0xd7,0x03,0x05,0xfe,0x03,0x00,0x01,0x04,0x05]
; GCN-NEXT:    v_perm_b32 v5, v1, v0, 0x5040100 ; encoding: [0x05,0x00,0x44,0xd7,0x01,0x01,0xfe,0x03,0x00,0x01,0x04,0x05]
; GCN-NEXT:    image_msaa_load v[0:3], [v5, v4], rsrcidx(s0) dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x47,0x20,0x20,0xe5,0x00,0x00,0x01,0x00,0x05,0x04,0x00,0x00]
; GCN-NEXT:    s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GCN-NEXT:    ; return to shader part epilog
main_body:
  %v = call <4 x float> @llvm.amdgcn.image.msaa.load.2darraymsaa.v4f32.i16(i32 4, i16 %s, i16 %t, i16 %slice, i16 %fragid, i32 %rsrc, i32 0, i32 0)
  ret <4 x float> %v
}