llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s

declare float @llvm.amdgcn.cubetc(float, float, float) #0

define amdgpu_ps float @test_cubetc_vvv(float %a, float %b, float %c) #1 {
; GCN-LABEL: test_cubetc_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    v_cubetc_f32 v0, v0, v1, v2
; GCN-NEXT:    ; return to shader part epilog
  %result = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
  ret float %result
}

define amdgpu_ps float @test_cubetc_sss(float inreg %a, float inreg %b, float inreg %c) #1 {
; GCN-LABEL: test_cubetc_sss:
; GCN:       ; %bb.0:
; GCN-NEXT:    v_mov_b32_e32 v0, s1
; GCN-NEXT:    v_mov_b32_e32 v1, s2
; GCN-NEXT:    v_cubetc_f32 v0, s0, v0, v1
; GCN-NEXT:    ; return to shader part epilog
  %result = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
  ret float %result
}

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }