| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=amdgpu9.00--amdpal < %s | FileCheck -check-prefix=GFX9 %s |
| ; RUN: llc -mtriple=amdgpu10.30--amdpal < %s | FileCheck -check-prefix=GFX10 %s |
| ; RUN: llc -mtriple=amdgpu11.00--amdpal < %s | FileCheck -check-prefix=GFX11 %s |
| ; RUN: llc -mtriple=amdgpu9.50--amdpal < %s | FileCheck -check-prefix=GFX950 %s |
| ; RUN: llc -mtriple=amdgpu6.00--amdpal < %s | FileCheck -check-prefix=GFX6 %s |
| |
| ; Test that redundant inf/nan checks are folded into frexp instructions. |
| ; The AMDGPU frexp instructions already return 0 for inf/nan inputs. |
| ; This optimization should NOT apply on GFX6 (Southern Islands) which has hasFractBug. |
| |
| ; Pattern 1: select (fcmp uno x, 0), 0, (frexp_exp x) |
| ; NaN check - should fold to just frexp_exp |
| define i32 @frexp_nan_clamp_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Commuted form: select (fcmp ord x, 0), frexp, 0 |
| define i32 @frexp_ord_clamp_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_ord_clamp_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_ord_clamp_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_ord_clamp_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_ord_clamp_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_ord_clamp_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_ord = fcmp ord float %x, 0.0 |
| %result = select i1 %is_ord, i32 %exp, i32 0 |
| ret i32 %result |
| } |
| |
| ; Pattern 2: select (fcmp oeq |x|, inf), 0, (frexp_exp x) |
| ; Inf check - should fold to just frexp_exp |
| define i32 @frexp_inf_clamp_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_inf_clamp_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_inf_clamp_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0| |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_inf_clamp_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0| |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_inf_clamp_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: s_mov_b32 s0, 0x7f800000 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_inf_clamp_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %abs = call float @llvm.fabs.f32(float %x) |
| %is_inf = fcmp oeq float %abs, +inf |
| %result = select i1 %is_inf, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Commuted form: fcmp one |x|, inf (not inf check -> select frexp) |
| define i32 @frexp_not_inf_clamp_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_not_inf_clamp_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: s_movk_i32 s4, 0x1f8 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_not_inf_clamp_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_not_inf_clamp_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_not_inf_clamp_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: s_movk_i32 s0, 0x1f8 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_not_inf_clamp_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: s_movk_i32 s6, 0x1f8 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, s[6:7], s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %abs = call float @llvm.fabs.f32(float %x) |
| %is_not_inf = fcmp one float %abs, +inf |
| %result = select i1 %is_not_inf, i32 %exp, i32 0 |
| ret i32 %result |
| } |
| |
| ; Pattern 3: select (fcmp ueq |x|, inf), 0, (frexp_exp x) |
| ; Inf-or-NaN check - should fold to just frexp_exp |
| define i32 @frexp_inf_or_nan_clamp_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_inf_or_nan_clamp_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: s_movk_i32 s4, 0x1f8 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_class_f32_e64 vcc, v0, s4 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_inf_or_nan_clamp_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_inf_or_nan_clamp_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_inf_or_nan_clamp_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: s_movk_i32 s0, 0x1f8 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_class_f32_e64 vcc, v0, s0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_inf_or_nan_clamp_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: s_movk_i32 s6, 0x1f8 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_class_f32_e64 s[6:7], v0, s6 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, s[6:7], s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %abs = call float @llvm.fabs.f32(float %x) |
| %is_non_finite = fcmp ueq float %abs, +inf |
| %result = select i1 %is_non_finite, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Test with frexp_mant instead of frexp_exp |
| define float @frexp_nan_clamp_mant_f32(float %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_mant_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_mant_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_mant_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_mant_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_mant_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %mant = extractvalue { float, i32 } %frexp, 0 |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, float 0.0, float %mant |
| ret float %result |
| } |
| |
| ; Test f64 |
| define i32 @frexp_nan_clamp_exp_f64(double %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_f64: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1] |
| ; GFX9-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1] |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_f64: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1] |
| ; GFX10-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1] |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_f64: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1] |
| ; GFX11-NEXT: v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1] |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_f64: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1] |
| ; GFX950-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[0:1] |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_f64: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1 |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7ff00000 |
| ; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, s4, v2 |
| ; GFX6-NEXT: v_cmp_o_f64_e64 s[4:5], v[0:1], v[0:1] |
| ; GFX6-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1] |
| ; GFX6-NEXT: s_and_b64 vcc, s[4:5], vcc |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { double, i32 } @llvm.frexp.f64.i32(double %x) |
| %exp = extractvalue { double, i32 } %frexp, 1 |
| %is_nan = fcmp uno double %x, 0.0 |
| %result = select i1 %is_nan, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Test f16 |
| define i16 @frexp_nan_clamp_exp_f16(half %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_f16: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v0.l |
| ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v0.h, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_f16: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_f16: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { half, i16 } @llvm.frexp.f16.i16(half %x) |
| %exp = extractvalue { half, i16 } %frexp, 1 |
| %is_nan = fcmp uno half %x, 0.0 |
| %result = select i1 %is_nan, i16 0, i16 %exp |
| ret i16 %result |
| } |
| |
| ; Test bfloat16 |
| define i16 @frexp_nan_clamp_exp_bf16(bfloat %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_bf16: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v1.l, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_bf16: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_bf16: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { bfloat, i16 } @llvm.frexp.bf16.i16(bfloat %x) |
| %exp = extractvalue { bfloat, i16 } %frexp, 1 |
| %is_nan = fcmp uno bfloat %x, 0.0 |
| %result = select i1 %is_nan, i16 0, i16 %exp |
| ret i16 %result |
| } |
| |
| ; Test v2f32 vector case |
| define <2 x i32> @frexp_nan_clamp_exp_v2f32(<2 x float> %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_v2f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_v2f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v3, v1 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_v2f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v2, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_v2f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_v2f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s6, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %x) |
| %exp = extractvalue { <2 x float>, <2 x i32> } %frexp, 1 |
| %is_nan = fcmp uno <2 x float> %x, zeroinitializer |
| %result = select <2 x i1> %is_nan, <2 x i32> zeroinitializer, <2 x i32> %exp |
| ret <2 x i32> %result |
| } |
| |
| ; Test v2f16 vector case |
| define <2 x i16> @frexp_nan_clamp_exp_v2f16(<2 x half> %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i16_f16_e32 v2, v0 |
| ; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc |
| ; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 |
| ; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_v2f16: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f16_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_frexp_exp_i16_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo |
| ; GFX10-NEXT: v_cmp_o_f16_sdwa vcc_lo, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc_lo |
| ; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v0 |
| ; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v0.l |
| ; GFX11-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v2.l |
| ; GFX11-NEXT: v_cmp_o_f16_e64 s0, v2.l, v2.l |
| ; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v0.h, vcc_lo |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b16 v0.h, 0, v1.l, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_v2f16: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i16_f16_e32 v2, v0 |
| ; GFX950-NEXT: v_cmp_o_f16_e32 vcc, v0, v0 |
| ; GFX950-NEXT: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 |
| ; GFX950-NEXT: s_mov_b32 s0, 0x5040100 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc |
| ; GFX950-NEXT: v_cmp_o_f16_sdwa vcc, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: v_perm_b32 v0, v0, v2, s0 |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_v2f16: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; GFX6-NEXT: s_mov_b32 s6, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, s6 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 |
| ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 |
| ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { <2 x half>, <2 x i16> } @llvm.frexp.v2f16.v2i16(<2 x half> %x) |
| %exp = extractvalue { <2 x half>, <2 x i16> } %frexp, 1 |
| %is_nan = fcmp uno <2 x half> %x, zeroinitializer |
| %result = select <2 x i1> %is_nan, <2 x i16> zeroinitializer, <2 x i16> %exp |
| ret <2 x i16> %result |
| } |
| |
| ; Test v2bf16 vector case |
| define <2 x i16> @frexp_nan_clamp_exp_v2bf16(<2 x bfloat> %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_exp_v2bf16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX9-NEXT: s_mov_b32 s4, 0x5040100 |
| ; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_exp_v2bf16: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1 |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc_lo |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo |
| ; GFX10-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_exp_v2bf16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e64 s0, v1, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b16 v0.h, 0, v3.l, vcc_lo |
| ; GFX11-NEXT: v_cndmask_b16 v0.l, 0, v2.l, s0 |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_exp_v2bf16: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 |
| ; GFX950-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX950-NEXT: s_mov_b32 s0, 0x5040100 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX950-NEXT: v_perm_b32 v0, v1, v0, s0 |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_exp_v2bf16: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v0 |
| ; GFX6-NEXT: s_mov_b32 s6, 0x7f800000 |
| ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, s6 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v3, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[6:7] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc |
| ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0 |
| ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 |
| ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0 |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { <2 x bfloat>, <2 x i16> } @llvm.frexp.v2bf16.v2i16(<2 x bfloat> %x) |
| %exp = extractvalue { <2 x bfloat>, <2 x i16> } %frexp, 1 |
| %is_nan = fcmp uno <2 x bfloat> %x, zeroinitializer |
| %result = select <2 x i1> %is_nan, <2 x i16> zeroinitializer, <2 x i16> %exp |
| ret <2 x i16> %result |
| } |
| |
| ; Test with amdgcn.frexp.exp intrinsic directly |
| define i32 @frexp_nan_clamp_amdgcn_exp_f32(float %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_amdgcn_exp_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_amdgcn_exp_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_amdgcn_exp_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_amdgcn_exp_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_amdgcn_exp_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %x) |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Test with amdgcn.frexp.mant intrinsic directly |
| define float @frexp_nan_clamp_amdgcn_mant_f32(float %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_amdgcn_mant_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_amdgcn_mant_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_amdgcn_mant_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_amdgcn_mant_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_amdgcn_mant_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: v_frexp_mant_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %mant = call float @llvm.amdgcn.frexp.mant.f32(float %x) |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, float 0.0, float %mant |
| ret float %result |
| } |
| |
| ; Test optimization applied to both mant and exp from the same frexp (most realistic case) |
| define { float, i32 } @frexp_nan_clamp_both_f32(float %x) { |
| ; GFX9-LABEL: frexp_nan_clamp_both_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_frexp_mant_f32_e32 v2, v0 |
| ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc |
| ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_both_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_frexp_mant_f32_e32 v2, v0 |
| ; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo |
| ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_both_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_frexp_mant_f32_e32 v2, v0 |
| ; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) |
| ; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc_lo |
| ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_both_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_frexp_mant_f32_e32 v2, v0 |
| ; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc |
| ; GFX950-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_both_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 |
| ; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc |
| ; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc |
| ; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc |
| ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %mant = extractvalue { float, i32 } %frexp, 0 |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_nan = fcmp uno float %x, 0.0 |
| %mant_result = select i1 %is_nan, float 0.0, float %mant |
| %exp_result = select i1 %is_nan, i32 0, i32 %exp |
| %result0 = insertvalue { float, i32 } poison, float %mant_result, 0 |
| %result1 = insertvalue { float, i32 } %result0, i32 %exp_result, 1 |
| ret { float, i32 } %result1 |
| } |
| |
| ; Test with copysign - should still fold since frexp ignores sign |
| define i32 @frexp_nan_clamp_copysign_f32(float %x, float %sign) { |
| ; GFX9-LABEL: frexp_nan_clamp_copysign_f32: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_clamp_copysign_f32: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_clamp_copysign_f32: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_clamp_copysign_f32: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_clamp_copysign_f32: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_brev_b32 s4, -2 |
| ; GFX6-NEXT: v_bfi_b32 v1, s4, v0, v1 |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %copysign = call float @llvm.copysign.f32(float %x, float %sign) |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %copysign) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Negative test: different input to frexp vs comparison |
| define i32 @frexp_nan_different_input(float %x, float %y) { |
| ; GFX9-LABEL: frexp_nan_different_input: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_different_input: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_different_input: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_different_input: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_different_input: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v1, v1 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_nan = fcmp uno float %y, 0.0 |
| %result = select i1 %is_nan, i32 0, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Negative test: non-zero constant in select |
| define i32 @frexp_nan_nonzero_const(float %x) { |
| ; GFX9-LABEL: frexp_nan_nonzero_const: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_nan_nonzero_const: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_nan_nonzero_const: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_nan_nonzero_const: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_nan_nonzero_const: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc |
| ; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0 |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 42, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_nan = fcmp uno float %x, 0.0 |
| %result = select i1 %is_nan, i32 42, i32 %exp |
| ret i32 %result |
| } |
| |
| ; Negative test: unrelated comparison (not inf/nan test) |
| define i32 @frexp_lt_zero_not_folded(float %x) { |
| ; GFX9-LABEL: frexp_lt_zero_not_folded: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX9-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 |
| ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX9-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX10-LABEL: frexp_lt_zero_not_folded: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX10-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 |
| ; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: frexp_lt_zero_not_folded: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX950-LABEL: frexp_lt_zero_not_folded: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX950-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX950-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 |
| ; GFX950-NEXT: s_nop 1 |
| ; GFX950-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX950-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX6-LABEL: frexp_lt_zero_not_folded: |
| ; GFX6: ; %bb.0: |
| ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX6-NEXT: s_mov_b32 s4, 0x7f800000 |
| ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4 |
| ; GFX6-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v0 |
| ; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 |
| ; GFX6-NEXT: s_and_b64 vcc, vcc, s[4:5] |
| ; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc |
| ; GFX6-NEXT: s_setpc_b64 s[30:31] |
| %frexp = call { float, i32 } @llvm.frexp.f32.i32(float %x) |
| %exp = extractvalue { float, i32 } %frexp, 1 |
| %is_lt_zero = fcmp olt float %x, 0.0 |
| %result = select i1 %is_lt_zero, i32 0, i32 %exp |
| ret i32 %result |
| } |
