llvm/test/CodeGen/AMDGPU/freeze-scalar-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck %s

; Test scalarization of a vector load wrapped in a single-use freeze.

define i32 @one_use_of_freeze(ptr addrspace(1) %p) {
; CHECK-LABEL: one_use_of_freeze:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mov_b32 s7, 0xf000
; CHECK-NEXT:    s_mov_b32 s4, s6
; CHECK-NEXT:    s_mov_b32 s5, s6
; CHECK-NEXT:    buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %load = load <2 x i32>, ptr addrspace(1) %p
  %freeze = freeze <2 x i32> %load
  %extract = extractelement <2 x i32> %freeze, i64 0
  ret i32 %extract
}

define i32 @no_use_of_freeze(ptr addrspace(1) %p) {
; CHECK-LABEL: no_use_of_freeze:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mov_b32 s7, 0xf000
; CHECK-NEXT:    s_mov_b32 s4, s6
; CHECK-NEXT:    s_mov_b32 s5, s6
; CHECK-NEXT:    buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %load = load <2 x i32>, ptr addrspace(1) %p
  %extract = extractelement <2 x i32> %load, i64 0
  ret i32 %extract
}

define i32 @multiple_use_of_freeze(ptr addrspace(1) %p) {
; CHECK-LABEL: multiple_use_of_freeze:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mov_b32 s7, 0xf000
; CHECK-NEXT:    s_mov_b32 s4, s6
; CHECK-NEXT:    s_mov_b32 s5, s6
; CHECK-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %load = load <2 x i32>, ptr addrspace(1) %p
  %freeze = freeze <2 x i32> %load
  %extract1 = extractelement <2 x i32> %freeze, i64 0
  %extract2 = extractelement <2 x i32> %freeze, i64 1
  %sum = add i32 %extract1, %extract2
  ret i32 %sum
}