llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s

define void @repro(<6 x i32> %a, i32 %i) {
; CHECK-LABEL: repro:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v6
; CHECK-NEXT:    v_cndmask_b32_e32 v7, v0, v1, vcc
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 2, v6
; CHECK-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
; CHECK-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 4, v6
; CHECK-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 5, v6
; CHECK-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; CHECK-NEXT:    v_xor_b32_e32 v1, v2, v1
; CHECK-NEXT:    v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT:    s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %r0 = shufflevector <6 x i32> %a, <6 x i32> poison, <6 x i32> <i32 0, i32 0, i32 poison, i32 0, i32 0, i32 1>
  %l0 = extractelement <6 x i32> %a, i32 %i
  %s = insertelement <6 x i32> poison, i32 %l0, i32 %i
  %r2 = shufflevector <6 x i32> %s, <6 x i32> poison, <6 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 0, i32 0>
  %d = xor <6 x i32> %r2, %r0
  %l = extractelement <6 x i32> %d, i32 %i
  %c = icmp ne i32 %l, 0
  br i1 %c, label %t, label %r
t:
  switch i32 0, label %r []
r:
  ret void
}