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llvm/llvm-project.git/refs/heads/main/./llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
blob: f1a38ead76ff305dc7fbd9f2642101a6954af3bd [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck -check-prefix=SDAG-GFX1150 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL-GFX1150 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=SDAG-GFX1200 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL-GFX1200 %s
define amdgpu_vs void @f32_olt(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_olt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_lt_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_olt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lt_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_olt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_lt_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_olt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lt_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp olt float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_oeq(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_oeq:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_eq_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_oeq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_eq_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_oeq:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_eq_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_oeq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_eq_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oeq float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ole(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ole:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_le_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ole:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ole:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_le_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ole:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ole float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ogt(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ogt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_gt_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ogt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_gt_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ogt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_gt_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ogt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_gt_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ogt float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_one(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_one:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_lg_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_one:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lg_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_one:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_lg_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_one:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lg_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp one float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_oge(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_oge:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_ge_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_oge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ge_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_oge:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_ge_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_oge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ge_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oge float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ord(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ord:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_o_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ord:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_o_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ord:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_o_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ord:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_o_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ord float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_uno(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_uno:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_u_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_uno:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_u_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_uno:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_u_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_uno:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_u_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uno float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ult(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ult:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nge_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ult:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nge_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ult:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nge_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ult:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nge_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ult float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ueq(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ueq:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nlg_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ueq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ueq:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nlg_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ueq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ueq float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ule(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ule:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_ngt_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ule:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ngt_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ule:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_ngt_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ule:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ngt_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ule float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_ugt(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_ugt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nle_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_ugt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nle_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_ugt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nle_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_ugt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nle_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ugt float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_une(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_une:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_neq_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_une:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_neq_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_une:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_neq_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_une:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_neq_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp une float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f32_uge(ptr addrspace(1) inreg %out, float inreg %a, float inreg %b) {
; SDAG-GFX1150-LABEL: f32_uge:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nlt_f32 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f32_uge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlt_f32 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f32_uge:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nlt_f32 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f32_uge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlt_f32 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uge float %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_olt(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_olt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_lt_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_olt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lt_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_olt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_lt_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_olt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lt_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp olt half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_oeq(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_oeq:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_eq_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_oeq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_eq_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_oeq:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_eq_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_oeq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_eq_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oeq half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ole(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ole:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_le_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ole:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_le_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ole:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_le_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ole:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_le_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ole half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ogt(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ogt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_gt_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ogt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_gt_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ogt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_gt_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ogt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_gt_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ogt half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_one(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_one:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_lg_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_one:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_lg_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_one:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_lg_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_one:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_lg_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp one half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_oge(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_oge:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_ge_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_oge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ge_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_oge:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_ge_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_oge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ge_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp oge half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ord(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ord:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_o_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ord:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_o_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ord:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_o_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ord:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_o_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ord half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_uno(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_uno:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_u_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_uno:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_u_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_uno:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_u_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_uno:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_u_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uno half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ult(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ult:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nge_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ult:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nge_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ult:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nge_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ult:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nge_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ult half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ueq(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ueq:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nlg_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ueq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlg_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ueq:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nlg_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ueq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlg_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ueq half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ule(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ule:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_ngt_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ule:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_ngt_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ule:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_ngt_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ule:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_ngt_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ule half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_ugt(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_ugt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nle_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_ugt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nle_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_ugt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nle_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_ugt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nle_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp ugt half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_une(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_une:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_neq_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_une:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_neq_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_une:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_neq_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_une:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_neq_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp une half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define amdgpu_vs void @f16_uge(ptr addrspace(1) inreg %out, half inreg %a, half inreg %b) {
; SDAG-GFX1150-LABEL: f16_uge:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_cmp_nlt_f16 s2, s3
; SDAG-GFX1150-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1150-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1150-NEXT: s_endpgm
;
; GISEL-GFX1150-LABEL: f16_uge:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_cmp_nlt_f16 s2, s3
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1150-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1150-NEXT: s_endpgm
;
; SDAG-GFX1200-LABEL: f16_uge:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_cmp_nlt_f16 s2, s3
; SDAG-GFX1200-NEXT: v_mov_b32_e32 v0, 0
; SDAG-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; SDAG-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
; SDAG-GFX1200-NEXT: global_store_b32 v0, v1, s[0:1]
; SDAG-GFX1200-NEXT: s_endpgm
;
; GISEL-GFX1200-LABEL: f16_uge:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_cmp_nlt_f16 s2, s3
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, -1, 0
; GISEL-GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1200-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX1200-NEXT: global_store_b32 v1, v0, s[0:1]
; GISEL-GFX1200-NEXT: s_endpgm
entry:
%0 = fcmp uge half %a, %b
%1 = sext i1 %0 to i32
store i32 %1, ptr addrspace(1) %out
ret void
}
define <8 x i1> @vector_f32_ole() {
; SDAG-GFX1150-LABEL: vector_f32_ole:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; SDAG-GFX1150-NEXT: s_clause 0x1
; SDAG-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1150-NEXT: global_load_b128 v[4:7], v[4:5], off
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(1)
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0)
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1150-LABEL: vector_f32_ole:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; GISEL-GFX1150-NEXT: s_clause 0x1
; GISEL-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1150-NEXT: global_load_b128 v[4:7], v[4:5], off
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(1)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s4, v4
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s0, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s5, v5
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s6, v6
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s7, v7
; GISEL-GFX1150-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s2, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s3, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s4, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1150-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s5, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s6, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GISEL-GFX1150-NEXT: s_cselect_b32 s6, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_le_f32 s7, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s7, 1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GISEL-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1200-LABEL: vector_f32_ole:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1200-NEXT: s_wait_expcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX1200-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_kmcnt 0x0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; SDAG-GFX1200-NEXT: s_clause 0x1
; SDAG-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1200-NEXT: global_load_b128 v[4:7], v[4:5], off
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x1
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x0
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1200-LABEL: vector_f32_ole:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1200-NEXT: s_wait_expcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX1200-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; GISEL-GFX1200-NEXT: s_clause 0x1
; GISEL-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1200-NEXT: global_load_b128 v[4:7], v[4:5], off
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s4, v4
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s0, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s5, v5
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s6, v6
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s7, v7
; GISEL-GFX1200-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s2, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s3, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s4, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1200-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s5, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s6, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GISEL-GFX1200-NEXT: s_cselect_b32 s6, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_le_f32 s7, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s7, 1, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GISEL-GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%LGV = load <8 x float>, ptr addrspace(1) null, align 32
%C = fcmp ole <8 x float> %LGV, zeroinitializer
ret <8 x i1> %C
}
define <4 x i1> @vector_f32_ogt() {
; SDAG-GFX1150-LABEL: vector_f32_ogt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0)
; SDAG-GFX1150-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1150-LABEL: vector_f32_ogt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1150-NEXT: s_cmp_gt_f32 s0, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_gt_f32 s1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_gt_f32 s2, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_gt_f32 s3, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1200-LABEL: vector_f32_ogt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1200-NEXT: s_wait_expcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX1200-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_kmcnt 0x0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x0
; SDAG-GFX1200-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1200-LABEL: vector_f32_ogt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1200-NEXT: s_wait_expcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX1200-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1200-NEXT: s_cmp_gt_f32 s0, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_gt_f32 s1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_gt_f32 s2, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_gt_f32 s3, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%LGV = load <4 x float>, ptr addrspace(1) null, align 16
%C = fcmp ogt <4 x float> %LGV, zeroinitializer
ret <4 x i1> %C
}
define <32 x i1> @vector_f32_ueq() {
; SDAG-GFX1150-LABEL: vector_f32_ueq:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; SDAG-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
; SDAG-GFX1150-NEXT: s_clause 0x1
; SDAG-GFX1150-NEXT: global_load_b128 v[4:7], v[4:5], off
; SDAG-GFX1150-NEXT: global_load_b128 v[8:11], v[8:9], off
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; SDAG-GFX1150-NEXT: global_load_b128 v[12:15], v[12:13], off
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; SDAG-GFX1150-NEXT: global_load_b128 v[16:19], v[16:17], off
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
; SDAG-GFX1150-NEXT: s_clause 0x2
; SDAG-GFX1150-NEXT: global_load_b128 v[20:23], v[20:21], off
; SDAG-GFX1150-NEXT: global_load_b128 v[24:27], v[24:25], off
; SDAG-GFX1150-NEXT: global_load_b128 v[28:31], v[28:29], off
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(7)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(6)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(5)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(4)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(3)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(2)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(1)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0)
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1150-LABEL: vector_f32_ueq:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; GISEL-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
; GISEL-GFX1150-NEXT: s_clause 0x1
; GISEL-GFX1150-NEXT: global_load_b128 v[4:7], v[4:5], off
; GISEL-GFX1150-NEXT: global_load_b128 v[8:11], v[8:9], off
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; GISEL-GFX1150-NEXT: global_load_b128 v[12:15], v[12:13], off
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; GISEL-GFX1150-NEXT: global_load_b128 v[16:19], v[16:17], off
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
; GISEL-GFX1150-NEXT: s_clause 0x2
; GISEL-GFX1150-NEXT: global_load_b128 v[20:23], v[20:21], off
; GISEL-GFX1150-NEXT: global_load_b128 v[24:27], v[24:25], off
; GISEL-GFX1150-NEXT: global_load_b128 v[28:31], v[28:29], off
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(7)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(6)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s4, v4
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s0, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s5, v5
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s6, v6
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s7, v7
; GISEL-GFX1150-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s1, 0
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(5)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s8, v8
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s9, v9
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s10, v10
; GISEL-GFX1150-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s2, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s11, v11
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(4)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s12, v12
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s13, v13
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s3, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s14, v14
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s15, v15
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(3)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s16, v16
; GISEL-GFX1150-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s4, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s17, v17
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s18, v18
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s19, v19
; GISEL-GFX1150-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s5, 0
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(2)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s20, v20
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s21, v21
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s22, v22
; GISEL-GFX1150-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s6, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s23, v23
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(1)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s24, v24
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s25, v25
; GISEL-GFX1150-NEXT: s_cselect_b32 s6, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s7, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s26, v26
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s27, v27
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s28, v28
; GISEL-GFX1150-NEXT: s_cselect_b32 s7, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s8, 0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s29, v29
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s40, v30
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s41, v31
; GISEL-GFX1150-NEXT: s_cselect_b32 s8, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s9, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1150-NEXT: s_cselect_b32 s9, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s10, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GISEL-GFX1150-NEXT: s_cselect_b32 s10, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s11, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GISEL-GFX1150-NEXT: s_cselect_b32 s11, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s12, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GISEL-GFX1150-NEXT: s_cselect_b32 s12, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s13, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s13, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s14, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GISEL-GFX1150-NEXT: s_cselect_b32 s14, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s15, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s15, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s16, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GISEL-GFX1150-NEXT: s_cselect_b32 s16, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s17, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s17, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s18, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GISEL-GFX1150-NEXT: s_cselect_b32 s18, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s19, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s19, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s20, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GISEL-GFX1150-NEXT: s_cselect_b32 s20, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s21, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s21, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s22, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GISEL-GFX1150-NEXT: s_cselect_b32 s22, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s23, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s23, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s24, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GISEL-GFX1150-NEXT: s_cselect_b32 s24, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s25, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s25, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s26, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GISEL-GFX1150-NEXT: s_cselect_b32 s26, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s27, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s27, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s28, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GISEL-GFX1150-NEXT: s_cselect_b32 s28, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s29, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s29, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s40, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GISEL-GFX1150-NEXT: s_cselect_b32 s40, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nlg_f32 s41, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s41, 1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v30, s40 :: v_dual_mov_b32 v31, s41
; GISEL-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1200-LABEL: vector_f32_ueq:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1200-NEXT: s_wait_expcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX1200-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_kmcnt 0x0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; SDAG-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
; SDAG-GFX1200-NEXT: s_clause 0x1
; SDAG-GFX1200-NEXT: global_load_b128 v[4:7], v[4:5], off
; SDAG-GFX1200-NEXT: global_load_b128 v[8:11], v[8:9], off
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; SDAG-GFX1200-NEXT: global_load_b128 v[12:15], v[12:13], off
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; SDAG-GFX1200-NEXT: global_load_b128 v[16:19], v[16:17], off
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
; SDAG-GFX1200-NEXT: s_clause 0x2
; SDAG-GFX1200-NEXT: global_load_b128 v[20:23], v[20:21], off
; SDAG-GFX1200-NEXT: global_load_b128 v[24:27], v[24:25], off
; SDAG-GFX1200-NEXT: global_load_b128 v[28:31], v[28:29], off
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x7
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x6
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x5
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x4
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x3
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x2
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x1
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x0
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1200-LABEL: vector_f32_ueq:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1200-NEXT: s_wait_expcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX1200-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; GISEL-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
; GISEL-GFX1200-NEXT: s_clause 0x1
; GISEL-GFX1200-NEXT: global_load_b128 v[4:7], v[4:5], off
; GISEL-GFX1200-NEXT: global_load_b128 v[8:11], v[8:9], off
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; GISEL-GFX1200-NEXT: global_load_b128 v[12:15], v[12:13], off
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; GISEL-GFX1200-NEXT: global_load_b128 v[16:19], v[16:17], off
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
; GISEL-GFX1200-NEXT: s_clause 0x2
; GISEL-GFX1200-NEXT: global_load_b128 v[20:23], v[20:21], off
; GISEL-GFX1200-NEXT: global_load_b128 v[24:27], v[24:25], off
; GISEL-GFX1200-NEXT: global_load_b128 v[28:31], v[28:29], off
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x7
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x6
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s4, v4
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s0, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s5, v5
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s6, v6
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s7, v7
; GISEL-GFX1200-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s1, 0
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x5
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s8, v8
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s9, v9
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s10, v10
; GISEL-GFX1200-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s2, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s11, v11
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x4
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s12, v12
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s13, v13
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s3, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s14, v14
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s15, v15
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x3
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s16, v16
; GISEL-GFX1200-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s4, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s17, v17
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s18, v18
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s19, v19
; GISEL-GFX1200-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s5, 0
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x2
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s20, v20
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s21, v21
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s22, v22
; GISEL-GFX1200-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s6, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s23, v23
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s24, v24
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s25, v25
; GISEL-GFX1200-NEXT: s_cselect_b32 s6, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s7, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s26, v26
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s27, v27
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s28, v28
; GISEL-GFX1200-NEXT: s_cselect_b32 s7, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s8, 0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s29, v29
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s40, v30
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s41, v31
; GISEL-GFX1200-NEXT: s_cselect_b32 s8, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s9, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1200-NEXT: s_cselect_b32 s9, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s10, 0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GISEL-GFX1200-NEXT: s_cselect_b32 s10, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s11, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GISEL-GFX1200-NEXT: s_cselect_b32 s11, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s12, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GISEL-GFX1200-NEXT: s_cselect_b32 s12, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s13, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s13, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s14, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GISEL-GFX1200-NEXT: s_cselect_b32 s14, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s15, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s15, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s16, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GISEL-GFX1200-NEXT: s_cselect_b32 s16, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s17, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s17, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s18, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GISEL-GFX1200-NEXT: s_cselect_b32 s18, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s19, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s19, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s20, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GISEL-GFX1200-NEXT: s_cselect_b32 s20, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s21, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s21, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s22, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GISEL-GFX1200-NEXT: s_cselect_b32 s22, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s23, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s23, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s24, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GISEL-GFX1200-NEXT: s_cselect_b32 s24, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s25, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s25, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s26, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GISEL-GFX1200-NEXT: s_cselect_b32 s26, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s27, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s27, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s28, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GISEL-GFX1200-NEXT: s_cselect_b32 s28, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s29, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s29, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s40, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GISEL-GFX1200-NEXT: s_cselect_b32 s40, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nlg_f32 s41, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s41, 1, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v30, s40 :: v_dual_mov_b32 v31, s41
; GISEL-GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%LGV = load <32 x float>, ptr addrspace(1) null, align 128
%C = fcmp ueq <32 x float> %LGV, zeroinitializer
ret <32 x i1> %C
}
define <4 x i1> @vector_f32_ugt() {
; SDAG-GFX1150-LABEL: vector_f32_ugt:
; SDAG-GFX1150: ; %bb.0: ; %entry
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1150-NEXT: s_waitcnt vmcnt(0)
; SDAG-GFX1150-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1150-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1150-LABEL: vector_f32_ugt:
; GISEL-GFX1150: ; %bb.0: ; %entry
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1150-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1150-NEXT: s_waitcnt vmcnt(0)
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1150-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1150-NEXT: s_cmp_nle_f32 s0, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nle_f32 s1, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nle_f32 s2, 0
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1150-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1150-NEXT: s_cmp_nle_f32 s3, 0
; GISEL-GFX1150-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1150-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-GFX1150-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1150-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1200-LABEL: vector_f32_ugt:
; SDAG-GFX1200: ; %bb.0: ; %entry
; SDAG-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; SDAG-GFX1200-NEXT: s_wait_expcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_samplecnt 0x0
; SDAG-GFX1200-NEXT: s_wait_bvhcnt 0x0
; SDAG-GFX1200-NEXT: s_wait_kmcnt 0x0
; SDAG-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; SDAG-GFX1200-NEXT: s_wait_loadcnt 0x0
; SDAG-GFX1200-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
; SDAG-GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; SDAG-GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; SDAG-GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1200-LABEL: vector_f32_ugt:
; GISEL-GFX1200: ; %bb.0: ; %entry
; GISEL-GFX1200-NEXT: s_wait_loadcnt_dscnt 0x0
; GISEL-GFX1200-NEXT: s_wait_expcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_samplecnt 0x0
; GISEL-GFX1200-NEXT: s_wait_bvhcnt 0x0
; GISEL-GFX1200-NEXT: s_wait_kmcnt 0x0
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GISEL-GFX1200-NEXT: global_load_b128 v[0:3], v[0:1], off
; GISEL-GFX1200-NEXT: s_wait_loadcnt 0x0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s0, v0
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s1, v1
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s2, v2
; GISEL-GFX1200-NEXT: v_readfirstlane_b32 s3, v3
; GISEL-GFX1200-NEXT: s_cmp_nle_f32 s0, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s0, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nle_f32 s1, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s1, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nle_f32 s2, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GISEL-GFX1200-NEXT: s_cselect_b32 s2, 1, 0
; GISEL-GFX1200-NEXT: s_cmp_nle_f32 s3, 0
; GISEL-GFX1200-NEXT: s_cselect_b32 s3, 1, 0
; GISEL-GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GISEL-GFX1200-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GISEL-GFX1200-NEXT: s_setpc_b64 s[30:31]
entry:
%LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
%C = fcmp ugt <4 x float> %LGV1, zeroinitializer
ret <4 x i1> %C
}