llvm/test/CodeGen/AMDGPU/convergent.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6

# machine-sink must not sink WMMA and PERMLANE instructions.
# Ensure that WMMA, PERMLANE, and DPP instructions are marked as convergent to prevent
# machine-sink from sinking them.

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx12-generic -run-pass=machine-sink %s -o - | FileCheck %s

################################################################################
# WMMA instructions
################################################################################

---
name:            test_V_WMMA_F32_16X16X16_F16_w32_threeaddr
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_WMMA_F32_16X16X16_F16_w32_threeaddr
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   early-clobber %3:vreg_256 = V_WMMA_F32_16X16X16_F16_w32_threeaddr 8, [[DEF]], 8, [[DEF1]], 8, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vreg_256 = COPY %3.sub1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vreg_128 = IMPLICIT_DEF
    %1:vreg_128 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    early-clobber %3:vreg_256 = V_WMMA_F32_16X16X16_F16_w32_threeaddr 8, %0:vreg_128, 8, %1:vreg_128, 8, 0, 0, 0, implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vreg_256 = COPY %3.sub1:vreg_256

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0

...

---
name:            test_V_WMMA_F32_16X16X16_F16_twoaddr_w32
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_WMMA_F32_16X16X16_F16_twoaddr_w32
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vsrc:vreg_256 = IMPLICIT_DEF
  ; CHECK-NEXT:   %ssrc:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   early-clobber %vdst:vreg_256 = V_WMMA_F32_16X16X16_F16_twoaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc, 0, 0, implicit $exec
  ; CHECK-NEXT:   %sdst:sreg_32 = SI_IF %ssrc, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vcopy:vgpr_32 = COPY %vdst.sub0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF %sdst, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %vsrc:vreg_256 = IMPLICIT_DEF
    %ssrc:sreg_32 = IMPLICIT_DEF
    early-clobber %vdst:vreg_256 = V_WMMA_F32_16X16X16_F16_twoaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc, 0, 0, implicit $exec
    %sdst:sreg_32 = SI_IF %ssrc:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1
  bb.1:
    %vcopy:vgpr_32 = COPY %vdst.sub0
  bb.2:
    SI_END_CF %sdst:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...

---
name:            test_V_WMMA_I32_16X16X16_IU8_twoaddr_w32
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_WMMA_I32_16X16X16_IU8_twoaddr_w32
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vsrc:vreg_128 = IMPLICIT_DEF
  ; CHECK-NEXT:   %vsrc2:vreg_256 = IMPLICIT_DEF
  ; CHECK-NEXT:   %ssrc:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   early-clobber %vdst:vreg_256 = V_WMMA_I32_16X16X16_IU8_twoaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc2, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   %sdst:sreg_32 = SI_IF %ssrc, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vcopy:vgpr_32 = COPY %vdst.sub0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF %sdst, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %vsrc:vreg_128 = IMPLICIT_DEF
    %vsrc2:vreg_256 = IMPLICIT_DEF
    %ssrc:sreg_32 = IMPLICIT_DEF
    early-clobber %vdst:vreg_256 = V_WMMA_I32_16X16X16_IU8_twoaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc2, 0, 0, 0, implicit $exec
    %sdst:sreg_32 = SI_IF %ssrc:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1
  bb.1:
    %vcopy:vgpr_32 = COPY %vdst.sub0
  bb.2:
    SI_END_CF %sdst:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...

---
name:            test_V_WMMA_BF16_16X16X16_BF16_threeaddr_w32
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_WMMA_BF16_16X16X16_BF16_threeaddr_w32
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vsrc:vreg_256 = IMPLICIT_DEF
  ; CHECK-NEXT:   %ssrc:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   early-clobber %vdst:vreg_256 = V_WMMA_BF16_16X16X16_BF16_threeaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc, 0, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   %sdst:sreg_32 = SI_IF %ssrc, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vcopy:vgpr_32 = COPY %vdst.sub0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF %sdst, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %vsrc:vreg_256 = IMPLICIT_DEF
    %ssrc:sreg_32 = IMPLICIT_DEF
    early-clobber %vdst:vreg_256 = V_WMMA_BF16_16X16X16_BF16_threeaddr_w32 8, %vsrc, 8, %vsrc, 8, %vsrc, 0, 0, 0, 0, implicit $exec
    %sdst:sreg_32 = SI_IF %ssrc:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1
  bb.1:
    %vcopy:vgpr_32 = COPY %vdst.sub0
  bb.2:
    SI_END_CF %sdst:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...

---
name:            test_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vsrc256:vreg_256 = IMPLICIT_DEF
  ; CHECK-NEXT:   %vsrc512:vreg_512 = IMPLICIT_DEF
  ; CHECK-NEXT:   %ssrc:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   early-clobber %vdst:vreg_256 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr %vsrc512, %vsrc512, 8, %vsrc256, 0, 0, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   %sdst:sreg_32 = SI_IF %ssrc, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %vcopy:vgpr_32 = COPY %vdst.sub0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF %sdst, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %vsrc256:vreg_256 = IMPLICIT_DEF
    %vsrc512:vreg_512 = IMPLICIT_DEF
    %ssrc:sreg_32 = IMPLICIT_DEF
    early-clobber %vdst:vreg_256 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr %vsrc512, %vsrc512, 8, %vsrc256, 0, 0, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, implicit $exec
    %sdst:sreg_32 = SI_IF %ssrc:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1
  bb.1:
    %vcopy:vgpr_32 = COPY %vdst.sub0
  bb.2:
    SI_END_CF %sdst:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...

################################################################################
# PERMLANE instructions
################################################################################

---
name:            test_V_PERMLANE_XOR_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE_XOR_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE_XOR_B32_e64 [[DEF]], [[DEF1]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE_XOR_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    %3:vgpr_32 = V_PERMLANE_XOR_B32_e64 %0:vgpr_32, %1:sreg_32, 0, implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vgpr_32 = COPY %3:vgpr_32

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE_UP_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE_UP_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE_UP_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE_UP_B32_e64 [[DEF]], [[DEF1]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE_UP_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    %3:vgpr_32 = V_PERMLANE_UP_B32_e64 %0:vgpr_32, %1:sreg_32, 0, implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vgpr_32 = COPY %3:vgpr_32

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE_DOWN_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE_DOWN_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE_DOWN_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE_DOWN_B32_e64 [[DEF]], [[DEF1]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE_DOWN_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    %3:vgpr_32 = V_PERMLANE_DOWN_B32_e64 %0:vgpr_32, %1:sreg_32, 0, implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vgpr_32 = COPY %3:vgpr_32

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE_BCAST_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE_BCAST_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE_BCAST_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE_BCAST_B32_e64 [[DEF]], [[DEF1]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE_BCAST_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    %3:vgpr_32 = V_PERMLANE_BCAST_B32_e64 %0:vgpr_32, %1:sreg_32, 0, implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vgpr_32 = COPY %3:vgpr_32

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE_IDX_GEN_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE_IDX_GEN_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE_IDX_GEN_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE_IDX_GEN_B32_e64 [[DEF]], [[DEF1]], implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF2]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE_IDX_GEN_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF
    %3:vgpr_32 = V_PERMLANE_IDX_GEN_B32_e64 %0:vgpr_32, %1:sreg_32,  implicit $exec
    %4:sreg_32 = SI_IF %2:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %5:vgpr_32 = COPY %3:vgpr_32

  bb.2:
    SI_END_CF %4:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANEX_VAR_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANEX_VAR_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANEX16_VAR_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANEX16_VAR_B32_e64 0, [[DEF]], 0, [[DEF]], [[DEF]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANEX16_VAR_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_PERMLANEX16_VAR_B32_e64 0, %0:vgpr_32, 0, %0:vgpr_32, %0:vgpr_32, 0, implicit $exec
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE64_B32
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE64_B32
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE64_B32_:%[0-9]+]]:vgpr_32 = V_PERMLANE64_B32 [[DEF]], implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE64_B32_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_PERMLANE64_B32 %0:vgpr_32, implicit $exec
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_PERMLANE16_VAR_B32_e64
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_PERMLANE16_VAR_B32_e64
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_PERMLANE16_VAR_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANE16_VAR_B32_e64 0, [[DEF]], 0, [[DEF]], [[DEF]], 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_PERMLANE16_VAR_B32_e64_]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_PERMLANE16_VAR_B32_e64 0, %0:vgpr_32, 0, %0:vgpr_32, %0:vgpr_32, 0, implicit $exec
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...

################################################################################
# DPP instructions
################################################################################

---
name:            test_V_DOT2C_F32_BF16_dpp_vi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_DOT2C_F32_BF16_dpp_vi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_DOT2C_F32_BF16_dpp_vi:%[0-9]+]]:vgpr_32 = V_DOT2C_F32_BF16_dpp_vi 8, [[DEF]], [[DEF]], [[DEF]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $mode
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_DOT2C_F32_BF16_dpp_vi]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_DOT2C_F32_BF16_dpp_vi 8, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, 0, 0, 0, 0, implicit $exec, implicit $mode
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_DOT2C_F32_F16_dpp_vi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_DOT2C_F32_F16_dpp_vi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_DOT2C_F32_F16_dpp_vi:%[0-9]+]]:vgpr_32 = V_DOT2C_F32_F16_dpp_vi 8, [[DEF]], [[DEF]], [[DEF]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $mode
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_DOT2C_F32_F16_dpp_vi]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_DOT2C_F32_F16_dpp_vi 8, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, 0, 0, 0, 0, implicit $exec, implicit $mode
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_DOT2C_I32_I16_dpp_vi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_DOT2C_I32_I16_dpp_vi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_DOT2C_I32_I16_dpp_vi:%[0-9]+]]:vgpr_32 = V_DOT2C_I32_I16_dpp_vi 8, [[DEF]], [[DEF]], [[DEF]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $mode
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_DOT2C_I32_I16_dpp_vi]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_DOT2C_I32_I16_dpp_vi 8, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, 0, 0, 0, 0, implicit $exec, implicit $mode
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_DOT4C_I32_I8_dpp_vi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_DOT4C_I32_I8_dpp_vi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_DOT4C_I32_I8_dpp_vi:%[0-9]+]]:vgpr_32 = V_DOT4C_I32_I8_dpp_vi 8, [[DEF]], [[DEF]], [[DEF]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $mode
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_DOT4C_I32_I8_dpp_vi]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_DOT4C_I32_I8_dpp_vi 8, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, 0, 0, 0, 0, implicit $exec, implicit $mode
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...
---
name:            test_V_DOT8C_I32_I4_dpp_vi
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_V_DOT8C_I32_I4_dpp_vi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[V_DOT8C_I32_I4_dpp_vi:%[0-9]+]]:vgpr_32 = V_DOT8C_I32_I4_dpp_vi 8, [[DEF]], [[DEF]], [[DEF]], [[DEF]], 0, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[DEF1]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_DOT8C_I32_I4_dpp_vi]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_DOT8C_I32_I4_dpp_vi 8, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, %0:vgpr_32, 0, 0, 0, 0, implicit $exec
    %3:sreg_32 = SI_IF %1:sreg_32, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    %4:vgpr_32 = COPY %2:vgpr_32

  bb.2:
    SI_END_CF %3:sreg_32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
    S_ENDPGM 0
...