llvm/test/CodeGen/AMDGPU/bf16-inline-int-const-opsel.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu12.50-amd-hsa -run-pass=si-fold-operands -o - %s | FileCheck %s

# An integer inline constant is sign-extended to 32 bits, so the operand reads
# as {hi: 0xffff, lo: 0xfffe} for -2. A half that wants 0xfffe has to select the
# low 16 bits, and one that wants the sign extension 0xffff has no encoding.

---
name: pk_add_bf16_neg_int_splat
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: pk_add_bf16_neg_int_splat
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_PK_ADD_BF16_:%[0-9]+]]:vgpr_32 = V_PK_ADD_BF16 8, [[COPY]], 0, -2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_BF16_]]
    %0:vgpr_32 = COPY $vgpr0
    %1:sreg_32 = S_MOV_B32 4294901758
    %2:vgpr_32 = V_PK_ADD_BF16 8, %0, 8, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    S_ENDPGM 0, implicit %2
...

---
name: pk_add_bf16_neg_int_lo_only
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: pk_add_bf16_neg_int_lo_only
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_PK_ADD_BF16_:%[0-9]+]]:vgpr_32 = V_PK_ADD_BF16 8, [[COPY]], 8, 65534, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_BF16_]]
    %0:vgpr_32 = COPY $vgpr0
    %1:sreg_32 = S_MOV_B32 65534
    %2:vgpr_32 = V_PK_ADD_BF16 8, %0, 8, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
    S_ENDPGM 0, implicit %2
...