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llvm/llvm-project.git/refs/heads/main/./llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.bf16.ll
blob: 8e1959e00131f9ddfb895806e1eb0729f4909b95 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX1250 %s
define amdgpu_ps i32 @fcmp_olt_bf16_vv(bfloat %a, bfloat %b) {
; GFX9-LABEL: fcmp_olt_bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_olt_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp olt bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_olt_bf16_ss(bfloat inreg %a, bfloat inreg %b) {
; GFX9-LABEL: fcmp_olt_bf16_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_olt_bf16_ss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_cmp_lt_f32 s0, s1
; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp olt bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_oeq_bf16_vv(bfloat %a, bfloat %b) {
; GFX9-LABEL: fcmp_oeq_bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cmp_eq_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_oeq_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp oeq bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_une_bf16_vv(bfloat %a, bfloat %b) {
; GFX9-LABEL: fcmp_une_bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cmp_neq_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_une_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cmp_neq_f32_e32 vcc_lo, v0, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp une bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_ord_bf16_vv(bfloat %a, bfloat %b) {
; GFX9-LABEL: fcmp_ord_bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_ord_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp ord bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_uno_bf16_ss(bfloat inreg %a, bfloat inreg %b) {
; GFX9-LABEL: fcmp_uno_bf16_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, s0, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_uno_bf16_ss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_cmp_u_f32 s0, s1
; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp uno bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps i32 @fcmp_uge_bf16_vs(bfloat %a, bfloat inreg %b) {
; GFX9-LABEL: fcmp_uge_bf16_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, s0, v0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_uge_bf16_vs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: v_cmp_ngt_f32_e32 vcc_lo, s0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp uge bfloat %a, %b
%r = zext i1 %cmp to i32
ret i32 %r
}
define amdgpu_ps bfloat @fcmp_ogt_select_bf16_vv(bfloat %a, bfloat %b) {
; GFX9-LABEL: fcmp_ogt_select_bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_ogt_select_bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v3, 16, v1
; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp ogt bfloat %a, %b
%r = select i1 %cmp, bfloat %a, bfloat %b
ret bfloat %r
}
define amdgpu_ps <2 x i32> @fcmp_ogt_v2bf16_vv(<2 x bfloat> %a, <2 x bfloat> %b) {
; GFX9-LABEL: fcmp_ogt_v2bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_ogt_v2bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX1250-NEXT: v_mov_b16_e32 v3.l, v1.h
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp ogt <2 x bfloat> %a, %b
%r = zext <2 x i1> %cmp to <2 x i32>
ret <2 x i32> %r
}
define amdgpu_ps <2 x i32> @fcmp_ogt_v2bf16_ss(<2 x bfloat> inreg %a, <2 x bfloat> inreg %b) {
; GFX9-LABEL: fcmp_ogt_v2bf16_ss:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
; GFX9-NEXT: s_lshr_b32 s2, s0, 16
; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_lshl_b32 s1, s2, 16
; GFX9-NEXT: s_lshl_b32 s2, s3, 16
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, s1, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_ogt_v2bf16_ss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: s_lshr_b32 s2, s0, 16
; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: s_lshl_b32 s3, s1, 16
; GFX1250-NEXT: s_lshr_b32 s1, s1, 16
; GFX1250-NEXT: s_cmp_gt_f32 s0, s3
; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_cmp_gt_f32 s2, s1
; GFX1250-NEXT: s_cselect_b32 s1, 1, 0
; GFX1250-NEXT: s_cmp_lg_u32 s0, 0
; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: s_cmp_lg_u32 s1, 0
; GFX1250-NEXT: s_cselect_b32 s1, 1, 0
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp ogt <2 x bfloat> %a, %b
%r = zext <2 x i1> %cmp to <2 x i32>
ret <2 x i32> %r
}
define amdgpu_ps <3 x i32> @fcmp_ole_v3bf16_vv(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX9-LABEL: fcmp_ole_v3bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_cmp_le_f32_e32 vcc, v0, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_le_f32_e32 vcc, v4, v5
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_le_f32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v2
; GFX9-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_ole_v3bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_mov_b16_e32 v4.l, v0.h
; GFX1250-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX1250-NEXT: v_dual_lshlrev_b32 v4, 16, v4 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX1250-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_le_f32_e32 vcc_lo, v4, v5
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_le_f32_e32 vcc_lo, v1, v3
; GFX1250-NEXT: v_readfirstlane_b32 s1, v2
; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp ole <3 x bfloat> %a, %b
%r = zext <3 x i1> %cmp to <3 x i32>
ret <3 x i32> %r
}
define amdgpu_ps <4 x i32> @fcmp_one_v4bf16_vv(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX9-LABEL: fcmp_one_v4bf16_vv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v0, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v4, v6
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_lg_f32_e32 vcc, v5, v7
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v2
; GFX9-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: fcmp_one_v4bf16_vv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX1250-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1250-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX1250-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX1250-NEXT: v_mov_b16_e32 v6.l, v1.h
; GFX1250-NEXT: v_mov_b16_e32 v7.l, v3.h
; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v5, 16, v5
; GFX1250-NEXT: v_cmp_lg_f32_e32 vcc_lo, v4, v2
; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX1250-NEXT: v_dual_lshlrev_b32 v6, 16, v6 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_lg_f32_e32 vcc_lo, v0, v5
; GFX1250-NEXT: v_readfirstlane_b32 s0, v2
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_lg_f32_e32 vcc_lo, v1, v3
; GFX1250-NEXT: v_readfirstlane_b32 s1, v0
; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX1250-NEXT: v_cmp_lg_f32_e32 vcc_lo, v6, v7
; GFX1250-NEXT: v_readfirstlane_b32 s2, v1
; GFX1250-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX1250-NEXT: v_readfirstlane_b32 s3, v3
; GFX1250-NEXT: ; return to shader part epilog
%cmp = fcmp one <4 x bfloat> %a, %b
%r = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %r
}