llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 -mattr=+v9.6a < %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -mattr=+v9.6a -global-isel=1 < %s | FileCheck %s

define void @test_keep_relaxed_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_relaxed_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    strb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 0, i32 8)
  ret void
}

define void @test_keep_relaxed_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_relaxed_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    strh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 0, i32 16)
  ret void
}

define void @test_keep_relaxed_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_relaxed_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    str w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 0, i32 32)
  ret void
}

define void @test_keep_relaxed_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_relaxed_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    str x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 0, i32 64)
  ret void
}

define void @test_keep_release_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_release_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlrb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 0, i32 8)
  ret void
}

define void @test_keep_release_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_release_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlrh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 0, i32 16)
  ret void
}

define void @test_keep_release_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_release_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlr w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 0, i32 32)
  ret void
}

define void @test_keep_release_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_release_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlr x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 0, i32 64)
  ret void
}

define void @test_keep_seqcst_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_seqcst_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlrb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 0, i32 8)
  ret void
}

define void @test_keep_seqcst_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_seqcst_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlrh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 0, i32 16)
  ret void
}

define void @test_keep_seqcst_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_seqcst_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlr w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 0, i32 32)
  ret void
}

define void @test_keep_seqcst_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_keep_seqcst_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh keep
; CHECK-NEXT:    stlr x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 0, i32 64)
  ret void
}

define void @test_strm_relaxed_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_relaxed_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    strb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 1, i32 8)
  ret void
}

define void @test_strm_relaxed_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_relaxed_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    strh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 1, i32 16)
  ret void
}

define void @test_strm_relaxed_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_relaxed_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    str w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 1, i32 32)
  ret void
}

define void @test_strm_relaxed_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_relaxed_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    str x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 0, i32 1, i32 64)
  ret void
}

define void @test_strm_release_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_release_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlrb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 1, i32 8)
  ret void
}

define void @test_strm_release_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_release_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlrh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 1, i32 16)
  ret void
}

define void @test_strm_release_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_release_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlr w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 1, i32 32)
  ret void
}

define void @test_strm_release_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_release_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlr x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 3, i32 1, i32 64)
  ret void
}

define void @test_strm_seqcst_i8(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_seqcst_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlrb w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 1, i32 8)
  ret void
}

define void @test_strm_seqcst_i16(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_seqcst_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlrh w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 1, i32 16)
  ret void
}

define void @test_strm_seqcst_i32(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_seqcst_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlr w1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 1, i32 32)
  ret void
}

define void @test_strm_seqcst_i64(ptr %p, i64 %v) {
; CHECK-LABEL: test_strm_seqcst_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    stshh strm
; CHECK-NEXT:    stlr x1, [x0]
; CHECK-NEXT:    ret
  call void @llvm.aarch64.stshh.atomic.store.p0(ptr %p, i64 %v, i32 5, i32 1, i32 64)
  ret void
}