llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i16 @testmhhs(half %x) {
; CHECK-LABEL: testmhhs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvt s0, h0
; CHECK-NEXT:    frintx s0, s0
; CHECK-NEXT:    fcvtzs w0, s0
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
  %conv = trunc i32 %0 to i16
  ret i16 %conv
}

define i32 @testmhws(half %x) {
; CHECK-LABEL: testmhws:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvt s0, h0
; CHECK-NEXT:    frintx s0, s0
; CHECK-NEXT:    fcvtzs w0, s0
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
  ret i32 %0
}

define i64 @testmhxs(half %x) {
; CHECK-LABEL: testmhxs:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fcvt s0, h0
; CHECK-NEXT:    frintx s0, s0
; CHECK-NEXT:    fcvtzs w8, s0
; CHECK-NEXT:    sxtw x0, w8
; CHECK-NEXT:    ret
entry:
  %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
  %conv = sext i32 %0 to i64
  ret i64 %conv
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}