llvm/test/CodeGen/AArch64/complex-deinterleaving-fma.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s --mattr=+complxnum,+neon -o - | FileCheck %s

target triple = "aarch64"

; Expected to transform
define <4 x float> @complex_mul_fmuladd(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: complex_mul_fmuladd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v2.2d, #0000000000000000
; CHECK-NEXT:    fcmla v2.4s, v0.4s, v1.4s, #0
; CHECK-NEXT:    fcmla v2.4s, v0.4s, v1.4s, #90
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %a.re = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %a.im = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
  %b.re = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %b.im = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>

  %t0 = fmul fast <2 x float> %a.im, %b.im
  %neg = fneg fast <2 x float> %t0
  %re = call fast <2 x float> @llvm.fmuladd.v2f32(<2 x float> %a.re, <2 x float> %b.re, <2 x float> %neg)
  %t1 = fmul fast <2 x float> %a.im, %b.re
  %im = call fast <2 x float> @llvm.fmuladd.v2f32(<2 x float> %a.re, <2 x float> %b.im, <2 x float> %t1)
  %r = shufflevector <2 x float> %re, <2 x float> %im, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  ret <4 x float> %r
}

define <4 x float> @complex_mul_fma_neg(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: complex_mul_fma_neg:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v2.2d, #0000000000000000
; CHECK-NEXT:    fcmla v2.4s, v0.4s, v1.4s, #180
; CHECK-NEXT:    fcmla v2.4s, v0.4s, v1.4s, #270
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %a.re = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %a.im = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
  %b.re = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %b.im = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>

  %neg0 = fneg fast <2 x float> %a.re
  %t0 = fmul fast <2 x float> %a.im, %b.im
  %re = call fast <2 x float> @llvm.fma.v2f32(<2 x float> %neg0, <2 x float> %b.re, <2 x float> %t0)
  %neg1 = fneg fast <2 x float> %a.re
  %t1 = fmul fast <2 x float> %a.im, %b.re
  %neg2 = fneg fast <2 x float> %t1
  %im = call fast <2 x float> @llvm.fma.v2f32(<2 x float> %neg1, <2 x float> %b.im, <2 x float> %neg2)
  %r = shufflevector <2 x float> %re, <2 x float> %im, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  ret <4 x float> %r
}

; Expected not to transform
define <4 x float> @complex_mul_fmuladd_no_fmf(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: complex_mul_fmuladd_no_fmf:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov d3, v0.d[1]
; CHECK-NEXT:    mov d4, v1.d[1]
; CHECK-NEXT:    movi v2.2s, #128, lsl #24
; CHECK-NEXT:    zip2 v5.2s, v0.2s, v3.2s
; CHECK-NEXT:    zip1 v6.2s, v1.2s, v4.2s
; CHECK-NEXT:    zip2 v1.2s, v1.2s, v4.2s
; CHECK-NEXT:    zip1 v0.2s, v0.2s, v3.2s
; CHECK-NEXT:    fmls v2.2s, v5.2s, v1.2s
; CHECK-NEXT:    fmul v3.2s, v5.2s, v6.2s
; CHECK-NEXT:    fmla v2.2s, v6.2s, v0.2s
; CHECK-NEXT:    fmla v3.2s, v1.2s, v0.2s
; CHECK-NEXT:    zip1 v0.4s, v2.4s, v3.4s
; CHECK-NEXT:    ret
  %a.re = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %a.im = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
  %b.re = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
  %b.im = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>

  %t0 = fmul <2 x float> %a.im, %b.im
  %neg = fneg <2 x float> %t0
  %re = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %a.re, <2 x float> %b.re, <2 x float> %neg)
  %t1 = fmul <2 x float> %a.im, %b.re
  %im = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %a.re, <2 x float> %b.im, <2 x float> %t1)
  %r = shufflevector <2 x float> %re, <2 x float> %im, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  ret <4 x float> %r
}

declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>)