llvm/test/CodeGen/AArch64/cmp-i256.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s

define i32 @icmp_slt_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_slt_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x0, x4
; CHECK-NEXT:    sbcs xzr, x1, x5
; CHECK-NEXT:    sbcs xzr, x2, x6
; CHECK-NEXT:    sbcs xzr, x3, x7
; CHECK-NEXT:    cset w0, lt
; CHECK-NEXT:    ret
  %c = icmp slt i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_sgt_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_sgt_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x4, x0
; CHECK-NEXT:    sbcs xzr, x5, x1
; CHECK-NEXT:    sbcs xzr, x6, x2
; CHECK-NEXT:    sbcs xzr, x7, x3
; CHECK-NEXT:    cset w0, lt
; CHECK-NEXT:    ret
  %c = icmp sgt i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_sle_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_sle_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x4, x0
; CHECK-NEXT:    sbcs xzr, x5, x1
; CHECK-NEXT:    sbcs xzr, x6, x2
; CHECK-NEXT:    sbcs xzr, x7, x3
; CHECK-NEXT:    cset w0, ge
; CHECK-NEXT:    ret
  %c = icmp sle i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_sge_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_sge_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x0, x4
; CHECK-NEXT:    sbcs xzr, x1, x5
; CHECK-NEXT:    sbcs xzr, x2, x6
; CHECK-NEXT:    sbcs xzr, x3, x7
; CHECK-NEXT:    cset w0, ge
; CHECK-NEXT:    ret
  %c = icmp sge i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_ult_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_ult_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x0, x4
; CHECK-NEXT:    sbcs xzr, x1, x5
; CHECK-NEXT:    sbcs xzr, x2, x6
; CHECK-NEXT:    sbcs xzr, x3, x7
; CHECK-NEXT:    cset w0, lo
; CHECK-NEXT:    ret
  %c = icmp ult i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_ugt_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_ugt_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x4, x0
; CHECK-NEXT:    sbcs xzr, x5, x1
; CHECK-NEXT:    sbcs xzr, x6, x2
; CHECK-NEXT:    sbcs xzr, x7, x3
; CHECK-NEXT:    cset w0, lo
; CHECK-NEXT:    ret
  %c = icmp ugt i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_ule_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_ule_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x4, x0
; CHECK-NEXT:    sbcs xzr, x5, x1
; CHECK-NEXT:    sbcs xzr, x6, x2
; CHECK-NEXT:    sbcs xzr, x7, x3
; CHECK-NEXT:    cset w0, hs
; CHECK-NEXT:    ret
  %c = icmp ule i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

define i32 @icmp_uge_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: icmp_uge_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x0, x4
; CHECK-NEXT:    sbcs xzr, x1, x5
; CHECK-NEXT:    sbcs xzr, x2, x6
; CHECK-NEXT:    sbcs xzr, x3, x7
; CHECK-NEXT:    cset w0, hs
; CHECK-NEXT:    ret
  %c = icmp uge i256 %a, %b
  %r = zext i1 %c to i32
  ret i32 %r
}

; Select based on i256 comparison
define i256 @select_slt_i256(i256 %a, i256 %b, i256 %x, i256 %y) nounwind {
; CHECK-LABEL: select_slt_i256:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmp x0, x4
; CHECK-NEXT:    add x8, sp, #32
; CHECK-NEXT:    mov x9, sp
; CHECK-NEXT:    sbcs xzr, x1, x5
; CHECK-NEXT:    sbcs xzr, x2, x6
; CHECK-NEXT:    sbcs xzr, x3, x7
; CHECK-NEXT:    csel x8, x9, x8, lt
; CHECK-NEXT:    ldp x0, x1, [x8]
; CHECK-NEXT:    ldp x2, x3, [x8, #16]
; CHECK-NEXT:    ret
  %c = icmp slt i256 %a, %b
  %r = select i1 %c, i256 %x, i256 %y
  ret i256 %r
}