| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 |
| // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-library -O1 -disable-llvm-passes -emit-llvm -finclude-default-header -o - %s | FileCheck %s |
| |
| // Check that lifetime.start for an inout argument temporary is emitted |
| // *before* the copy-in store, so that the store is within the lifetime |
| // and is not treated as undefined behavior. |
| |
| // CHECK-LABEL: define hidden void @_Z9incrementRi( |
| // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: [[ENTRY:.*:]] |
| // CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry() |
| // CHECK-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4, !tbaa [[INTPTR_TBAA7:![0-9]+]] |
| // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[I_ADDR]], align 4, !tbaa [[INTPTR_TBAA7]], !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] |
| // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[INT_TBAA12:![0-9]+]] |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK-NEXT: store i32 [[ADD]], ptr [[TMP1]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: ret void |
| // |
| void increment(inout int I) { I += 1; } |
| |
| // CHECK-LABEL: define hidden void @_Z5resetRi( |
| // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR0]] { |
| // CHECK-NEXT: [[ENTRY:.*:]] |
| // CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry() |
| // CHECK-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 4, !tbaa [[INTPTR_TBAA7]] |
| // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[I_ADDR]], align 4, !tbaa [[INTPTR_TBAA7]], !nonnull [[META10]], !align [[META11]] |
| // CHECK-NEXT: store i32 0, ptr [[TMP1]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: ret void |
| // |
| void reset(out int I) { I = 0; } |
| |
| // The lifetime.start must come before the copy-in load/store sequence. |
| // CHECK-LABEL: define hidden noundef i32 @_Z10inout_testi( |
| // CHECK-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] { |
| // CHECK-NEXT: [[ENTRY:.*:]] |
| // CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry() |
| // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[TMP]]) #[[ATTR3:[0-9]+]] |
| // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X_ADDR]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: call void @_Z9incrementRi(ptr noalias noundef nonnull align 4 dereferenceable(4) [[TMP]]) #[[ATTR4:[0-9]+]] [ "convergencectrl"(token [[TMP0]]) ] |
| // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: store i32 [[TMP2]], ptr [[X_ADDR]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[TMP]]) #[[ATTR3]] |
| // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_ADDR]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: ret i32 [[TMP3]] |
| // |
| int inout_test(int X) { |
| increment(X); |
| return X; |
| } |
| |
| // For `out` parameters there is no copy-in, so lifetime.start just needs |
| // to appear before the call with no intervening store to the temporary. |
| // CHECK-LABEL: define hidden noundef i32 @_Z8out_testv( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: [[ENTRY:.*:]] |
| // CHECK-NEXT: [[TMP0:%.*]] = call token @llvm.experimental.convergence.entry() |
| // CHECK-NEXT: [[X:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[X]]) #[[ATTR3]] |
| // CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[TMP]]) #[[ATTR3]] |
| // CHECK-NEXT: call void @_Z5resetRi(ptr noalias noundef nonnull align 4 dereferenceable(4) [[TMP]]) #[[ATTR4]] [ "convergencectrl"(token [[TMP0]]) ] |
| // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: store i32 [[TMP1]], ptr [[X]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[TMP]]) #[[ATTR3]] |
| // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4, !tbaa [[INT_TBAA12]] |
| // CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[X]]) #[[ATTR3]] |
| // CHECK-NEXT: ret i32 [[TMP2]] |
| // |
| int out_test() { |
| int X; |
| reset(X); |
| return X; |
| } |
| |
| //. |
| // CHECK: [[META4:![0-9]+]] = !{!"int", [[META5:![0-9]+]], i64 0} |
| // CHECK: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0} |
| // CHECK: [[META6]] = !{!"Simple C++ TBAA"} |
| // CHECK: [[INTPTR_TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0} |
| // CHECK: [[META8]] = !{!"p1 int", [[META9:![0-9]+]], i64 0} |
| // CHECK: [[META9]] = !{!"any pointer", [[META5]], i64 0} |
| // CHECK: [[META10]] = !{} |
| // CHECK: [[META11]] = !{i64 4} |
| // CHECK: [[INT_TBAA12]] = !{[[META4]], [[META4]], i64 0} |
| //. |
