[AArch64] Fix range check of R_AARCH64_TLSLE_ADD_TPREL_HI12
Summary:
An AArch64 LE relocation is a positive ("variant 1") offset. This
relocation is used to write the upper 12 bits of a 24-bit offset into an
add instruction:
add x0, x0, :tprel_hi12:v1
The comment in the ARM docs for R_AARCH64_TLSLE_ADD_TPREL_HI12 is:
"Set an ADD immediate field to bits [23:12] of X; check 0 <= X < 2^24."
Reviewers: javed.absar, espindola, ruiu, peter.smith, zatrazz
Reviewed By: ruiu
Subscribers: emaste, arichardson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D52525
git-svn-id: https://llvm.org/svn/llvm-project/lld/trunk@343144 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/ELF/Arch/AArch64.cpp b/ELF/Arch/AArch64.cpp
index 7a0d28e..be77109 100644
--- a/ELF/Arch/AArch64.cpp
+++ b/ELF/Arch/AArch64.cpp
@@ -346,7 +346,7 @@
or32le(Loc, (Val & 0xFFFC) << 3);
break;
case R_AARCH64_TLSLE_ADD_TPREL_HI12:
- checkInt(Loc, Val, 24, Type);
+ checkUInt(Loc, Val, 24, Type);
or32AArch64Imm(Loc, Val >> 12);
break;
case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
diff --git a/test/ELF/aarch64-tls-le.s b/test/ELF/aarch64-tls-le.s
index a77068d..85cd3be 100644
--- a/test/ELF/aarch64-tls-le.s
+++ b/test/ELF/aarch64-tls-le.s
@@ -13,6 +13,9 @@
mrs x0, TPIDR_EL0
add x0, x0, :tprel_hi12:v1
add x0, x0, :tprel_lo12_nc:v1
+ mrs x0, TPIDR_EL0
+ add x0, x0, :tprel_hi12:v2
+ add x0, x0, :tprel_lo12_nc:v2
# TCB size = 0x16 and foo is first element from TLS register.
#CHECK: Disassembly of section .text:
@@ -20,12 +23,26 @@
#CHECK: 210000: 40 d0 3b d5 mrs x0, TPIDR_EL0
#CHECK: 210004: 00 00 40 91 add x0, x0, #0, lsl #12
#CHECK: 210008: 00 40 00 91 add x0, x0, #16
+#CHECK: 21000c: 40 d0 3b d5 mrs x0, TPIDR_EL0
+#CHECK: 210010: 00 fc 7f 91 add x0, x0, #4095, lsl #12
+#CHECK: 210014: 00 e0 3f 91 add x0, x0, #4088
+
+.section .tbss,"awT",@nobits
.type v1,@object
-.section .tbss,"awT",@nobits
.globl v1
.p2align 2
v1:
.word 0
.size v1, 4
+# The current offset from the thread pointer is 20. Raise it to just below the
+# 24-bit limit.
+.space (0xfffff8 - 20)
+
+.type v2,@object
+.globl v2
+.p2align 2
+v2:
+.word 0
+.size v2, 4
