commit c09d70eb391667a1ab2a181c14ed8246c46e8779
author Craig Topper <craig.topper@intel.com> Mon Feb 04 04:44:20 2019 +0000
committer Craig Topper <craig.topper@intel.com> Mon Feb 04 04:44:20 2019 +0000
tree 8b4190e2f5735253fe796fc71e8b0a8acf4d038c
parent 7425230ea1dd5e529462c27110012b8f894bca3a

Recommit r352660 "[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7."

We now print ST0 as 'st' when generating the clobber list for MS inline assembly in clang. This matches what the gcc reg name list expects.

Original commit message:

This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.

Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.

Differential Revision: https://reviews.llvm.org/D57298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353016 91177308-0d34-0410-b5e6-96231b3b80d8