commit d4f7cbfea6a91329fb5bbb05e8b6266ee1bf535d
author Simon Pilgrim <llvm-dev@redking.me.uk> Sun Mar 24 16:30:35 2019 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Sun Mar 24 16:30:35 2019 +0000
tree 08673962d32bae3044afbd2fee20c81121fdb9ff
parent ff5f64e4c8e72159f06487684037dcd3eca2cd8e

[X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)

Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets).

Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356858 91177308-0d34-0410-b5e6-96231b3b80d8