Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.
In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.
Differential Revision: https://reviews.llvm.org/D43624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332240 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCMIPeephole.cpp b/lib/Target/PowerPC/PPCMIPeephole.cpp
index 6f44e3a..79bba98 100644
--- a/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -119,8 +119,8 @@
MRI = &MF->getRegInfo();
MDT = &getAnalysis<MachineDominatorTree>();
TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
- DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
- DEBUG(MF->dump());
+ LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
+ LLVM_DEBUG(MF->dump());
}
static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
@@ -238,8 +238,8 @@
if (TII->convertToImmediateForm(MI)) {
// We don't erase anything in case the def has other uses. Let DCE
// remove it if it can be removed.
- DEBUG(dbgs() << "Converted instruction to imm form: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
+ LLVM_DEBUG(MI.dump());
NumConvertedToImmediateForm++;
SomethingChanged = true;
Simplified = true;
@@ -324,10 +324,9 @@
};
if (DefMI && (Immed == 0 || Immed == 3)) {
if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) {
- DEBUG(dbgs()
- << "Optimizing load-and-splat/splat "
- "to load-and-splat/copy: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
+ "to load-and-splat/copy: ");
+ LLVM_DEBUG(MI.dump());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
@@ -346,10 +345,9 @@
TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
- DEBUG(dbgs()
- << "Optimizing splat/swap or splat/splat "
- "to splat/copy: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
+ "to splat/copy: ");
+ LLVM_DEBUG(MI.dump());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(1));
@@ -362,8 +360,8 @@
// parameter.
else if ((Immed == 0 || Immed == 3)
&& FeedImmed == 2 && FeedReg1 == FeedReg2) {
- DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
+ LLVM_DEBUG(MI.dump());
MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
MI.getOperand(3).setImm(3 - Immed);
@@ -373,8 +371,8 @@
// If this is a swap fed by a swap, we can replace it
// with a copy from the first swap's input.
else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
- DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
+ LLVM_DEBUG(MI.dump());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(DefMI->getOperand(1));
@@ -389,8 +387,8 @@
DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
ToErase = &MI;
Simplified = true;
- DEBUG(dbgs() << "Removing redundant splat: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
+ LLVM_DEBUG(MI.dump());
}
}
}
@@ -429,8 +427,8 @@
// If the instruction[s] that feed this splat have already splat
// the value, this splat is redundant.
if (AlreadySplat) {
- DEBUG(dbgs() << "Changing redundant splat to a copy: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
+ LLVM_DEBUG(MI.dump());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(MI.getOperand(OpNo));
@@ -448,14 +446,14 @@
if (ShiftOp1 == ShiftOp2) {
unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
if (MRI->hasOneNonDBGUse(ShiftRes)) {
- DEBUG(dbgs() << "Removing redundant shift: ");
- DEBUG(DefMI->dump());
+ LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
+ LLVM_DEBUG(DefMI->dump());
ToErase = DefMI;
}
Simplified = true;
- DEBUG(dbgs() << "Changing splat immediate from " << SplatImm <<
- " to " << NewElem << " in instruction: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
+ << " to " << NewElem << " in instruction: ");
+ LLVM_DEBUG(MI.dump());
MI.getOperand(1).setReg(ShiftOp1);
MI.getOperand(2).setImm(NewElem);
}
@@ -499,12 +497,12 @@
if (Use.getOperand(i).isReg() &&
Use.getOperand(i).getReg() == FRSPDefines)
Use.getOperand(i).setReg(ConvReg1);
- DEBUG(dbgs() << "Removing redundant FRSP:\n");
- DEBUG(RoundInstr->dump());
- DEBUG(dbgs() << "As it feeds instruction:\n");
- DEBUG(MI.dump());
- DEBUG(dbgs() << "Through instruction:\n");
- DEBUG(DefMI->dump());
+ LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n");
+ LLVM_DEBUG(RoundInstr->dump());
+ LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
+ LLVM_DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Through instruction:\n");
+ LLVM_DEBUG(DefMI->dump());
RoundInstr->eraseFromParent();
}
};
@@ -552,11 +550,11 @@
};
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
- DEBUG(dbgs() << "Zero-extending load\n");
- DEBUG(SrcMI->dump());
- DEBUG(dbgs() << "and sign-extension\n");
- DEBUG(MI.dump());
- DEBUG(dbgs() << "are merged into sign-extending load\n");
+ LLVM_DEBUG(dbgs() << "Zero-extending load\n");
+ LLVM_DEBUG(SrcMI->dump());
+ LLVM_DEBUG(dbgs() << "and sign-extension\n");
+ LLVM_DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
SrcMI->setDesc(TII->get(Opc));
SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
ToErase = &MI;
@@ -596,11 +594,11 @@
};
unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
isXForm(SrcMI->getOpcode()));
- DEBUG(dbgs() << "Zero-extending load\n");
- DEBUG(SrcMI->dump());
- DEBUG(dbgs() << "and sign-extension\n");
- DEBUG(MI.dump());
- DEBUG(dbgs() << "are merged into sign-extending load\n");
+ LLVM_DEBUG(dbgs() << "Zero-extending load\n");
+ LLVM_DEBUG(SrcMI->dump());
+ LLVM_DEBUG(dbgs() << "and sign-extension\n");
+ LLVM_DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
SrcMI->setDesc(TII->get(Opc));
SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
ToErase = &MI;
@@ -610,7 +608,7 @@
TII->isSignExtended(*SrcMI)) {
// We can eliminate EXTSW if the input is known to be already
// sign-extended.
- DEBUG(dbgs() << "Removing redundant sign-extension\n");
+ LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
unsigned TmpReg =
MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
@@ -661,7 +659,7 @@
unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
if (MI.getOperand(3).getImm() <= KnownZeroCount) {
- DEBUG(dbgs() << "Removing redundant zero-extension\n");
+ LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.addReg(SrcReg);
@@ -727,8 +725,8 @@
MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI);
for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
- DEBUG(dbgs() << "Optimizing LI to ADDI: ");
- DEBUG(LiMI->dump());
+ LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: ");
+ LLVM_DEBUG(LiMI->dump());
// There could be repeated registers in the PHI, e.g: %1 =
// PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
@@ -746,12 +744,12 @@
MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
.addReg(DominatorReg)
.addImm(LiImm); // restore the imm of LI
- DEBUG(LiMI->dump());
+ LLVM_DEBUG(LiMI->dump());
}
// Replace ADD with COPY
- DEBUG(dbgs() << "Optimizing ADD to COPY: ");
- DEBUG(MI.dump());
+ LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
+ LLVM_DEBUG(MI.dump());
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
MI.getOperand(0).getReg())
.add(Op1);
@@ -1197,11 +1195,11 @@
continue;
}
- DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
- DEBUG(CMPI1->dump());
- DEBUG(BI1->dump());
- DEBUG(CMPI2->dump());
- DEBUG(BI2->dump());
+ LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
+ LLVM_DEBUG(CMPI1->dump());
+ LLVM_DEBUG(BI1->dump());
+ LLVM_DEBUG(CMPI2->dump());
+ LLVM_DEBUG(BI2->dump());
// We adjust opcode, predicates and immediate as we determined above.
if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
@@ -1260,15 +1258,15 @@
BI2->getOperand(1).setIsKill(true);
BI1->getOperand(1).setIsKill(false);
- DEBUG(dbgs() << "into a compare and two branches:\n");
- DEBUG(CMPI1->dump());
- DEBUG(BI1->dump());
- DEBUG(BI2->dump());
+ LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
+ LLVM_DEBUG(CMPI1->dump());
+ LLVM_DEBUG(BI1->dump());
+ LLVM_DEBUG(BI2->dump());
if (IsPartiallyRedundant) {
- DEBUG(dbgs() << "The following compare is moved into "
- << printMBBReference(*MBBtoMoveCmp)
- << " to handle partial redundancy.\n");
- DEBUG(CMPI2->dump());
+ LLVM_DEBUG(dbgs() << "The following compare is moved into "
+ << printMBBReference(*MBBtoMoveCmp)
+ << " to handle partial redundancy.\n");
+ LLVM_DEBUG(CMPI2->dump());
}
Simplified = true;
