Reland "[ScalarEvolution] createSCEV(): recognize `udiv`/`urem` disguised as an `sdiv`/`srem`"
This reverts commit d3e3f36ff1151f565730977ac4f663a2ccee48ae,
which reverter the original commit 2c16100e6f72075564ea1f67fa5a82c269dafcd3,
but with polly tests now actually passing.
GitOrigin-RevId: a2619a60e4601c445e9ca6e16c76052e00d907ff
diff --git a/test/Isl/CodeGen/MemAccess/generate-all.ll b/test/Isl/CodeGen/MemAccess/generate-all.ll
index a3253ef..f9b07a9 100644
--- a/test/Isl/CodeGen/MemAccess/generate-all.ll
+++ b/test/Isl/CodeGen/MemAccess/generate-all.ll
@@ -9,11 +9,12 @@
; }
; SCEV: polly.stmt.bb2: ; preds = %polly.loop_header
-; SCEV-NEXT: %p_tmp = srem i64 %polly.indvar, 4
-; SCEV-NEXT: %p_tmp3 = getelementptr inbounds float, float* %A, i64 %p_tmp
-; SCEV-NEXT: %tmp4_p_scalar_ = load float, float* %p_tmp3, align 4, !alias.scope !0, !noalias !2
+; SCEV-NEXT: %0 = trunc i64 %polly.indvar to i2
+; SCEV-NEXT: %1 = zext i2 %0 to i64
+; SCEV-NEXT: %scevgep = getelementptr float, float* %A, i64 %1
+; SCEV-NEXT: %tmp4_p_scalar_ = load float, float* %scevgep, align 4, !alias.scope !0, !noalias !2
; SCEV-NEXT: %p_tmp5 = fadd float %tmp4_p_scalar_, 1.000000e+01
-; SCEV-NEXT: store float %p_tmp5, float* %p_tmp3, align 4, !alias.scope !0, !noalias !2
+; SCEV-NEXT: store float %p_tmp5, float* %scevgep, align 4, !alias.scope !0, !noalias !2
; SCEV-NEXT: %polly.indvar_next = add nsw i64 %polly.indvar, 1
; SCEV-NEXT: %polly.loop_cond = icmp sle i64 %polly.indvar_next, 99
; SCEV-NEXT: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit
diff --git a/test/ScopInfo/multidim_srem.ll b/test/ScopInfo/multidim_srem.ll
index 10673f4..f7f9616 100644
--- a/test/ScopInfo/multidim_srem.ll
+++ b/test/ScopInfo/multidim_srem.ll
@@ -14,11 +14,12 @@
; CHECK-NEXT: Schedule :=
; CHECK-NEXT: [n] -> { Stmt_for_body_8[i0, i1, i2] -> [i0, i1, i2] };
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK-NEXT: [n] -> { Stmt_for_body_8[i0, i1, i2] -> MemRef_A[o0, i1, i2] : (i0 + o0) mod 2 = 0 and 0 <= o0 <= 1 }
+; CHECK-NEXT: [n] -> { Stmt_for_body_8[i0, i1, i2] -> MemRef_A[1, i1, i2] : (1 + i0) mod 2 = 0; Stmt_for_body_8[i0, i1, i2] -> MemRef_A[0, i1, i2] : (i0) mod 2 = 0 };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
-; CHECK-NEXT: [n] -> { Stmt_for_body_8[i0, i1, i2] -> MemRef_A[o0, i1, i2] : (i0 + o0) mod 2 = 0 and 0 <= o0 <= 1 };
+; CHECK-NEXT: [n] -> { Stmt_for_body_8[i0, i1, i2] -> MemRef_A[1, i1, i2] : (1 + i0) mod 2 = 0; Stmt_for_body_8[i0, i1, i2] -> MemRef_A[0, i1, i2] : (i0) mod 2 = 0 };
; CHECK-NEXT: }
+
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
