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llvm / llvm-project / mlir
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  1. ac85a78 [mlir][AMDGPU] Avoid verifier crash in DPPOp on vector operand types (#178887) by Ayush Kumar Gaur · 24 hours ago main master
  2. f9de407 [mlir][Linalg] Promote lhs/rhs when vectorizing conv1D as outerproduct (#179883) by Abhishek Varma · 32 hours ago
  3. bc45779 [mlir][GPU] Verify known_{block,grid,cluster}_size is at least 1 (#179886) by woruyu · 35 hours ago
  4. f9de401 [MLIR][XeGPU] Propagate layout from anchor ops before Wg To Sg & Blocking Pass (#179490) by Nishant Patel · 2 days ago
  5. 743fb0d [MLIR][XeGPU] Fixing PR179016 minor issues (#180295) by Jianhui Li · 2 days ago

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.