[AMDGPU] Convert some tests to opaque pointers (NFC)
GitOrigin-RevId: bdf2fbba9cee60b4b260ff17e4f44c475c11e715
diff --git a/test/CodeGen/AMDGPU/fdot2.ll b/test/CodeGen/AMDGPU/fdot2.ll
index 7da5dbd..8573cd4 100644
--- a/test/CodeGen/AMDGPU/fdot2.ll
+++ b/test/CodeGen/AMDGPU/fdot2.ll
@@ -21,12 +21,12 @@
; GFX906-CONTRACT: v_mac_f16_e32
; GFX906-DENORM-CONTRACT: v_fma_f16
-define amdgpu_kernel void @dotproduct_f16(<2 x half> addrspace(1)* %src1,
- <2 x half> addrspace(1)* %src2,
- half addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @dotproduct_f16(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
- %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
+ %src1.vec = load <2 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <2 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%src2.el1 = extractelement <2 x half> %src2.vec, i64 0
@@ -36,10 +36,10 @@
%mul2 = fmul half %src1.el2, %src2.el2
%mul1 = fmul half %src1.el1, %src2.el1
- %acc = load half, half addrspace(1)* %dst, align 2
+ %acc = load half, ptr addrspace(1) %dst, align 2
%acc1 = fadd half %mul2, %acc
%acc2 = fadd half %mul1, %acc1
- store half %acc2, half addrspace(1)* %dst, align 2
+ store half %acc2, ptr addrspace(1) %dst, align 2
ret void
}
@@ -59,12 +59,12 @@
; GFX906-CONTRACT: v_dot2_f32_f16
; GFX906-DENORM-CONTRACT: v_dot2_f32_f16
-define amdgpu_kernel void @dotproduct_f16_f32(<2 x half> addrspace(1)* %src1,
- <2 x half> addrspace(1)* %src2,
- float addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @dotproduct_f16_f32(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
- %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
+ %src1.vec = load <2 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <2 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
@@ -78,10 +78,10 @@
%mul2 = fmul float %csrc1.el2, %csrc2.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
- %acc = load float, float addrspace(1)* %dst, align 4
+ %acc = load float, ptr addrspace(1) %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
- store float %acc2, float addrspace(1)* %dst, align 4
+ store float %acc2, ptr addrspace(1) %dst, align 4
ret void
}
@@ -99,12 +99,12 @@
; GFX906-CONTRACT: v_dot2_f32_f16
; GFX906-DENORM-CONTRACT: v_dot2_f32_f16
-define amdgpu_kernel void @dotproduct_diffvecorder(<2 x half> addrspace(1)* %src1,
- <2 x half> addrspace(1)* %src2,
- float addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @dotproduct_diffvecorder(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
- %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
+ %src1.vec = load <2 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <2 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
@@ -118,10 +118,10 @@
%mul2 = fmul float %csrc2.el2, %csrc1.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
- %acc = load float, float addrspace(1)* %dst, align 4
+ %acc = load float, ptr addrspace(1) %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
- store float %acc2, float addrspace(1)* %dst, align 4
+ store float %acc2, ptr addrspace(1) %dst, align 4
ret void
}
@@ -136,12 +136,12 @@
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
-define amdgpu_kernel void @dotproduct_v4f16(<4 x half> addrspace(1)* %src1,
- <4 x half> addrspace(1)* %src2,
- float addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @dotproduct_v4f16(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <4 x half>, <4 x half> addrspace(1)* %src1
- %src2.vec = load <4 x half>, <4 x half> addrspace(1)* %src2
+ %src1.vec = load <4 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <4 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <4 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
@@ -155,10 +155,10 @@
%mul2 = fmul float %csrc1.el2, %csrc2.el2
%mul1 = fmul float %csrc1.el1, %csrc2.el1
- %acc = load float, float addrspace(1)* %dst, align 4
+ %acc = load float, ptr addrspace(1) %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
- store float %acc2, float addrspace(1)* %dst, align 4
+ store float %acc2, ptr addrspace(1) %dst, align 4
ret void
}
@@ -173,12 +173,12 @@
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
-define amdgpu_kernel void @NotAdotproduct(<2 x half> addrspace(1)* %src1,
- <2 x half> addrspace(1)* %src2,
- float addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @NotAdotproduct(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
- %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
+ %src1.vec = load <2 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <2 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
@@ -192,10 +192,10 @@
%mul2 = fmul float %csrc1.el2, %csrc1.el1
%mul1 = fmul float %csrc2.el1, %csrc2.el2
- %acc = load float, float addrspace(1)* %dst, align 4
+ %acc = load float, ptr addrspace(1) %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
- store float %acc2, float addrspace(1)* %dst, align 4
+ store float %acc2, ptr addrspace(1) %dst, align 4
ret void
}
@@ -210,12 +210,12 @@
; GFX906-CONTRACT: v_fma_mix_f32
; GFX906-DENORM-CONTRACT: v_fma_mix_f32
-define amdgpu_kernel void @Diff_Idx_NotAdotproduct(<2 x half> addrspace(1)* %src1,
- <2 x half> addrspace(1)* %src2,
- float addrspace(1)* nocapture %dst) {
+define amdgpu_kernel void @Diff_Idx_NotAdotproduct(ptr addrspace(1) %src1,
+ ptr addrspace(1) %src2,
+ ptr addrspace(1) nocapture %dst) {
entry:
- %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
- %src2.vec = load <2 x half>, <2 x half> addrspace(1)* %src2
+ %src1.vec = load <2 x half>, ptr addrspace(1) %src1
+ %src2.vec = load <2 x half>, ptr addrspace(1) %src2
%src1.el1 = extractelement <2 x half> %src1.vec, i64 0
%csrc1.el1 = fpext half %src1.el1 to float
@@ -229,9 +229,9 @@
%mul2 = fmul float %csrc1.el2, %csrc2.el1
%mul1 = fmul float %csrc1.el1, %csrc2.el2
- %acc = load float, float addrspace(1)* %dst, align 4
+ %acc = load float, ptr addrspace(1) %dst, align 4
%acc1 = fadd float %mul2, %acc
%acc2 = fadd float %mul1, %acc1
- store float %acc2, float addrspace(1)* %dst, align 4
+ store float %acc2, ptr addrspace(1) %dst, align 4
ret void
}
