e8f829d3a87683ef5eca364dd9d04eb7a1a02dcd - llvm-project/llvm

commit	e8f829d3a87683ef5eca364dd9d04eb7a1a02dcd	[log] [tgz]
author	Visoiu Mistrih Francis <890283+francisvm@users.noreply.github.com>	Fri Sep 29 10:43:23 2023 -0700
committer	Copybara-Service <copybara-worker@google.com>	Fri Sep 29 10:46:51 2023 -0700
tree	552066a06c09d1407507231418cde29dbc5c4205
parent	b9530fb555684eb2bef896001ae1750c86b2898e [diff]

[test] -march -> -mtriple (#67741)

Similar to 806761a

GitOrigin-RevId: cc9ba5600e540fd4e059d20591917962a6df043d

test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/copy32.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/copy64.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir[diff]
test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir[diff]
test/CodeGen/RISCV/copy-frameindex.mir[diff]
test/CodeGen/RISCV/live-sp.mir[diff]
test/CodeGen/RISCV/machine-outliner-cfi.mir[diff]
test/CodeGen/RISCV/machine-outliner-position.mir[diff]
test/CodeGen/RISCV/machineoutliner-jumptable.mir[diff]
test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir[diff]
test/CodeGen/RISCV/machineoutliner.mir[diff]
test/CodeGen/RISCV/rvv/addi-scalable-offset.mir[diff]
test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir[diff]
test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir[diff]
test/CodeGen/RISCV/rvv/mask-reg-alloc.mir[diff]
test/CodeGen/RISCV/rvv/zvlsseg-spill.mir[diff]
test/CodeGen/RISCV/stack-inst-compress.mir[diff]
test/CodeGen/RISCV/stack-slot-coloring.mir[diff]
test/CodeGen/RISCV/verify-instr.mir[diff]
test/MachineVerifier/test_g_brindirect_is_indirect_branch.mir[diff]
test/MachineVerifier/test_g_brjt_is_indirect_branch.mir[diff]
test/Transforms/InterleavedAccess/RISCV/zvl32b.ll[diff]

41 files changed

tree: 552066a06c09d1407507231418cde29dbc5c4205