[RISCV] Fix scheduling info for compressed LD/ST of FP types. (#82339)
GitOrigin-RevId: d3fb596c9720b8bf192823730e9fccc3d86de9a8
diff --git a/lib/Target/RISCV/RISCVInstrInfoC.td b/lib/Target/RISCV/RISCVInstrInfoC.td
index 0713703..18d3834 100644
--- a/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -317,7 +317,7 @@
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
- Sched<[WriteFLD64, ReadMemBase]> {
+ Sched<[WriteFLD64, ReadFMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
let Inst{6-5} = imm{7-6};
@@ -334,7 +334,7 @@
let DecoderNamespace = "RISCV32Only_",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
- Sched<[WriteFLD32, ReadMemBase]> {
+ Sched<[WriteFLD32, ReadFMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
let Inst{6} = imm{2};
@@ -351,7 +351,7 @@
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
- Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
+ Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
let Inst{6-5} = imm{7-6};
@@ -368,7 +368,7 @@
let DecoderNamespace = "RISCV32Only_",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
- Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
+ Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
let Inst{6} = imm{2};
@@ -506,7 +506,7 @@
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
- Sched<[WriteFLD64, ReadMemBase]> {
+ Sched<[WriteFLD64, ReadFMemBase]> {
let Inst{6-5} = imm{4-3};
let Inst{4-2} = imm{8-6};
}
@@ -520,7 +520,7 @@
let DecoderNamespace = "RISCV32Only_",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
- Sched<[WriteFLD32, ReadMemBase]> {
+ Sched<[WriteFLD32, ReadFMemBase]> {
let Inst{6-4} = imm{4-2};
let Inst{3-2} = imm{7-6};
}
@@ -564,7 +564,7 @@
let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
- Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
+ Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
let Inst{12-10} = imm{5-3};
let Inst{9-7} = imm{8-6};
}
@@ -578,7 +578,7 @@
let DecoderNamespace = "RISCV32Only_",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
- Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
+ Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
let Inst{12-9} = imm{5-2};
let Inst{8-7} = imm{7-6};
}