c98d9c5cc5c60f9fac3eb30cb443c27ac6bfc785 - llvm-project/llvm

commit: c98d9c5cc5c60f9fac3eb30cb443c27ac6bfc785
[log] [tgz]
author: Matthew Devereau <matthew.devereau@arm.com>
Fri Sep 29 16:17:31 2023 +0100
committer: Copybara-Service <copybara-worker@google.com>
Fri Sep 29 08:24:09 2023 -0700
tree: cab0b7277a4166a358d5be09d164b385c96b5f2e
parent: ee7d0db3dc9473250035de87aa9beee6c5ce7449 [diff]

[AArch64][SME2][SVE2p1] Add PNR_3b regclass (#67785)

This patch adds the PNR_3b regclass for predicate-as-counter registers
0-7 and allows the Upl ASM constraint to use this register class.

GitOrigin-RevId: 6f5b372d593f1d08f6569a32f529b6bd5106237c

lib/Target/AArch64/AArch64ISelLowering.cpp[diff]
lib/Target/AArch64/AArch64RegisterInfo.td[diff]
test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll[diff]
test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll[diff]
test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir[diff]
test/CodeGen/AArch64/aarch64-sme2-asm.ll[diff]
test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll[diff]
test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir[diff]
test/CodeGen/AArch64/peephole-insvigpr.mir[diff]

9 files changed

tree: cab0b7277a4166a358d5be09d164b385c96b5f2e