[RISCV] Add another test case showing failure to use remw when the RHS has been zero extended from less than i32. NFC
GitOrigin-RevId: 038bd14712d149cb51a8e95eb7bbdcfa7753a555
diff --git a/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll b/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
index a60714f..c5b5472 100644
--- a/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ b/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -1123,6 +1123,18 @@
ret i32 %5
}
+define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b) nounwind {
+; RV64IM-LABEL: sext_i32_remw_sext_zext_i16:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: rem a0, a0, a1
+; RV64IM-NEXT: sext.w a0, a0
+; RV64IM-NEXT: ret
+ %1 = sext i16 %a to i32
+ %2 = zext i16 %b to i32
+ %3 = srem i32 %1, %2
+ ret i32 %3
+}
+
define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: aext_remuw_aext_aext:
; RV64IM: # %bb.0:
