| commit | b3f087752c406695b3b9e4c0da21695e8bb5f111 | [log] [tgz] |
|---|---|---|
| author | Tony Tye <Tony.Tye@amd.com> | Tue Feb 16 03:22:34 2021 +0000 |
| committer | Copybara-Service <copybara-worker@google.com> | Fri Feb 19 02:59:29 2021 -0800 |
| tree | 5a7fc5d57f06bb886f5698358acee6aae433797b | |
| parent | 9125a167f487d4bd94c1f664b64cf7c2f23106d9 [diff] |
[AMDGPU] Correct rmw atomics s_waitcnt generation The AMD GPU SIMemoryLegalizer was using the ordering address space rather than the instruction address space when determining the s_waitcnt to generate to ensure that a read-modify-write atomic has completed. This resulted in additional unnecessary counters being waited on. Differential Revision: https://reviews.llvm.org/D96743 GitOrigin-RevId: c62b737ad655f189cf76f4324ba04317133d6648