MIPSr6: Set FSELECT Legal for f64 (#173591)

FIX: #172459
Since SETCC returns i1 in IR level, and SEL_D needs f64, currently, we
expand FSELECT to:
   MTC1_D64
   SEL
which may generate needless mfc1 and mtc1.

In this patch, we add FGR64CC Register type, and support F32 to F64 in
MipsSEInstrInfo::copyPhysReg.
GitOrigin-RevId: 22c01f68739876505766769f72762053237fdcd9