[SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used. Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.
This particularly helps with llvmpipe.
Based on a patch by Richard Sandiford.
llvm-svn: 236523
GitOrigin-RevId: 80b3af7ab3f8e76507cc4491be1460f1b1d8adb2
diff --git a/test/CodeGen/SystemZ/vec-move-08.ll b/test/CodeGen/SystemZ/vec-move-08.ll
index 6148529..5396a1e 100644
--- a/test/CodeGen/SystemZ/vec-move-08.ll
+++ b/test/CodeGen/SystemZ/vec-move-08.ll
@@ -214,6 +214,59 @@
ret <2 x i64> %ret
}
+; Test v4f32 insertion into the first element.
+define <4 x float> @f21(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f21:
+; CHECK: vlef %v24, 0(%r2), 0
+; CHECK: br %r14
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 0
+ ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into the last element.
+define <4 x float> @f22(<4 x float> %val, float *%ptr) {
+; CHECK-LABEL: f22:
+; CHECK: vlef %v24, 0(%r2), 3
+; CHECK: br %r14
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 3
+ ret <4 x float> %ret
+}
+
+; Test v4f32 insertion with the highest in-range offset.
+define <4 x float> @f23(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f23:
+; CHECK: vlef %v24, 4092(%r2), 2
+; CHECK: br %r14
+ %ptr = getelementptr float, float *%base, i32 1023
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 2
+ ret <4 x float> %ret
+}
+
+; Test v4f32 insertion with the first ouf-of-range offset.
+define <4 x float> @f24(<4 x float> %val, float *%base) {
+; CHECK-LABEL: f24:
+; CHECK: aghi %r2, 4096
+; CHECK: vlef %v24, 0(%r2), 1
+; CHECK: br %r14
+ %ptr = getelementptr float, float *%base, i32 1024
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 1
+ ret <4 x float> %ret
+}
+
+; Test v4f32 insertion into a variable element.
+define <4 x float> @f25(<4 x float> %val, float *%ptr, i32 %index) {
+; CHECK-LABEL: f25:
+; CHECK-NOT: vlef
+; CHECK: br %r14
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 %index
+ ret <4 x float> %ret
+}
+
; Test v2f64 insertion into the first element.
define <2 x double> @f26(<2 x double> %val, double *%ptr) {
; CHECK-LABEL: f26:
@@ -336,6 +389,34 @@
ret <2 x i64> %ret
}
+; Test a v4f32 gather of the first element.
+define <4 x float> @f36(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f36:
+; CHECK: vgef %v24, 0(%v26,%r2), 0
+; CHECK: br %r14
+ %elem = extractelement <4 x i32> %index, i32 0
+ %ext = zext i32 %elem to i64
+ %add = add i64 %base, %ext
+ %ptr = inttoptr i64 %add to float *
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 0
+ ret <4 x float> %ret
+}
+
+; Test a v4f32 gather of the last element.
+define <4 x float> @f37(<4 x float> %val, <4 x i32> %index, i64 %base) {
+; CHECK-LABEL: f37:
+; CHECK: vgef %v24, 0(%v26,%r2), 3
+; CHECK: br %r14
+ %elem = extractelement <4 x i32> %index, i32 3
+ %ext = zext i32 %elem to i64
+ %add = add i64 %base, %ext
+ %ptr = inttoptr i64 %add to float *
+ %element = load float, float *%ptr
+ %ret = insertelement <4 x float> %val, float %element, i32 3
+ ret <4 x float> %ret
+}
+
; Test a v2f64 gather of the first element.
define <2 x double> @f38(<2 x double> %val, <2 x i64> %index, i64 %base) {
; CHECK-LABEL: f38:
