[RISCV] Add support for fixed vector sign/zero extend from mask types.

Due to vXi64 on RV32, I've directly emitted this using _VL ISD
opcodes. If it wasn't for that we could just use fixed vector
BUILD_VECTOR and VSELECT and let those each be legalized.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96910

GitOrigin-RevId: 792627be359e5d3386c4d8bb97eb1e5e5ec43b0c
2 files changed