0fe28b33ade2570464d5627fcb495a16cc726022 - llvm-project/llvm

commit: 0fe28b33ade2570464d5627fcb495a16cc726022
[log]
author: Sudharsan Veeravalli <quic_svs@quicinc.com>
Tue Jun 24 07:11:46 2025 +0530
committer: Copybara-Service <copybara-worker@google.com>
Mon Jun 23 18:47:39 2025 -0700
tree: 5b6762534e23724bd0c8445de3461125bd9e423e
parent: 4b0eb624ec9083512f682361e5acb635702457ea [diff]

[RISCV] Add ISel pattern for generating QC_BREV32 (#145288)

The `QC_BREV32` instruction reverses the bit order of `rs1` and writes
the result to `rd`

GitOrigin-RevId: 88b98d3367f3b1e8741f18789b567b141c8ef87b

lib/Target/RISCV/RISCVISelLowering.cpp[diff]
lib/Target/RISCV/RISCVInstrInfoXqci.td[diff]
test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll[Renamed from test/CodeGen/RISCV/xqcibm-cto-clo.ll - diff]

3 files changed

tree: 5b6762534e23724bd0c8445de3461125bd9e423e