[RISCV] Add missing hunk to #67889 to fix test failures
Without this, various CodeGen tests fail because a
RISCV::FCVT_D_W[_IN32X] machine node is created without the rounding
mode operand.
The relevant PR was committed as bf94ba39b65d1212ea84d5783b393280e1ce7478
GitOrigin-RevId: 0b0ed8f76a264c3677b8254d8d334de43600568f
diff --git a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 70b9041..e90b8d4 100644
--- a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -911,7 +911,13 @@
break;
}
- SDNode *Res = CurDAG->getMachineNode(Opc, DL, VT, Imm);
+ SDNode *Res;
+ if (Opc == RISCV::FCVT_D_W_IN32X || Opc == RISCV::FCVT_D_W)
+ Res = CurDAG->getMachineNode(
+ Opc, DL, VT, Imm,
+ CurDAG->getTargetConstant(RISCVFPRndMode::RNE, DL, XLenVT));
+ else
+ Res = CurDAG->getMachineNode(Opc, DL, VT, Imm);
// For f64 -0.0, we need to insert a fneg.d idiom.
if (NegZeroF64)
