[ELF] Inline isPPC64SmallCodeModelTocReloc which is only called once. NFC
GitOrigin-RevId: d71bb6a4091893b12d52947d4d4f774a672921bf
diff --git a/ELF/Arch/PPC64.cpp b/ELF/Arch/PPC64.cpp
index d1568de..d5e73ab 100644
--- a/ELF/Arch/PPC64.cpp
+++ b/ELF/Arch/PPC64.cpp
@@ -187,11 +187,6 @@
return 0;
}
-bool elf::isPPC64SmallCodeModelTocReloc(RelType type) {
- // The only small code model relocations that access the .toc section.
- return type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS;
-}
-
void elf::writePrefixedInstruction(uint8_t *loc, uint64_t insn) {
insn = config->isLE ? insn << 32 | insn >> 32 : insn;
write64(loc, insn);
diff --git a/ELF/Relocations.cpp b/ELF/Relocations.cpp
index 1d444a9..9c22ce7 100644
--- a/ELF/Relocations.cpp
+++ b/ELF/Relocations.cpp
@@ -1333,7 +1333,7 @@
// have got-based small code model relocs. The .toc sections get placed
// after the end of the linker allocated .got section and we do sort those
// so sections addressed with small code model relocations come first.
- if (isPPC64SmallCodeModelTocReloc(type))
+ if (type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS)
sec.file->ppc64SmallCodeModelTocRelocs = true;
// Record the TOC entry (.toc + addend) as not relaxable. See the comment in
diff --git a/ELF/Target.h b/ELF/Target.h
index abb769b..e0e9730 100644
--- a/ELF/Target.h
+++ b/ELF/Target.h
@@ -212,10 +212,6 @@
// to the local entry-point.
unsigned getPPC64GlobalEntryToLocalEntryOffset(uint8_t stOther);
-// Returns true if a relocation is a small code model relocation that accesses
-// the .toc section.
-bool isPPC64SmallCodeModelTocReloc(RelType type);
-
// Write a prefixed instruction, which is a 4-byte prefix followed by a 4-byte
// instruction (regardless of endianness). Therefore, the prefix is always in
// lower memory than the instruction.
