[libc][NFC] Remove headergen for the cacheline size macro.
We want to be able to build and test the string functions in contexts
like that of Fuchsia where LLVM pieces like tablegen are not available.
Since header generation uses tablegen, we are removing the dependency on
headergen here.
Reviewed By: gchatelet
Differential Revision: https://reviews.llvm.org/D97363
GitOrigin-RevId: 5f0800cc187a006e0424b9fd66985b39525d4478
diff --git a/src/string/memory_utils/CMakeLists.txt b/src/string/memory_utils/CMakeLists.txt
index 9aeeb2f..327031a 100644
--- a/src/string/memory_utils/CMakeLists.txt
+++ b/src/string/memory_utils/CMakeLists.txt
@@ -1,21 +1,7 @@
-add_gen_header(
- cacheline_size
- DEF_FILE
- cacheline_size.h.def
- GEN_HDR
- cacheline_size.h
- PARAMS
- machine_cacheline_size=cacheline_size_${LIBC_TARGET_MACHINE}.h.inc
- DATA_FILES
- cacheline_size_${LIBC_TARGET_MACHINE}.h.inc
-)
-
add_header_library(
memory_utils
HDRS
utils.h
memcpy_utils.h
memset_utils.h
- DEPENDS
- .cacheline_size
)
diff --git a/src/string/memory_utils/cacheline_size.h.def b/src/string/memory_utils/cacheline_size.h.def
deleted file mode 100644
index d2c05f1..0000000
--- a/src/string/memory_utils/cacheline_size.h.def
+++ /dev/null
@@ -1,27 +0,0 @@
-//===-- Cacheline Size Constant -------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIBC_SRC_MEMORY_CONSTANTS_H
-#define LLVM_LIBC_SRC_MEMORY_CONSTANTS_H
-
-// LLVM_LIBC_CACHELINE_SIZE
-//
-// Explicitly defines the size of the L1 cache for purposes of alignment.
-//
-// NOTE: this macro should be replaced with the following C++17 features, when
-// those are generally available:
-//
-// * `std::hardware_constructive_interference_size`
-// * `std::hardware_destructive_interference_size`
-//
-// See http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0154r1.html
-// for more information.
-
-%%include_file(${machine_cacheline_size})
-
-#endif // LLVM_LIBC_SRC_MEMORY_CONSTANTS_H
diff --git a/src/string/memory_utils/cacheline_size_aarch64.h.inc b/src/string/memory_utils/cacheline_size_aarch64.h.inc
deleted file mode 100644
index 34d8cef..0000000
--- a/src/string/memory_utils/cacheline_size_aarch64.h.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-// We would need to read special register ctr_el0 to find out L1 dcache size.
-// This value is a good estimate based on a real aarch64 machine.
-#define LLVM_LIBC_CACHELINE_SIZE 64
diff --git a/src/string/memory_utils/cacheline_size_arm.h.inc b/src/string/memory_utils/cacheline_size_arm.h.inc
deleted file mode 100644
index f3a43e0..0000000
--- a/src/string/memory_utils/cacheline_size_arm.h.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-// Cache line sizes for ARM: These values are not strictly correct since
-// cache line sizes depend on implementations, not architectures. There
-// are even implementations with cache line sizes configurable at boot
-// time.
-#if defined(__ARM_ARCH_5T__)
-#define LLVM_LIBC_CACHELINE_SIZE 32
-#elif defined(__ARM_ARCH_7A__)
-#define LLVM_LIBC_CACHELINE_SIZE 64
-#endif
diff --git a/src/string/memory_utils/cacheline_size_ppc64.h.inc b/src/string/memory_utils/cacheline_size_ppc64.h.inc
deleted file mode 100644
index 3c26994..0000000
--- a/src/string/memory_utils/cacheline_size_ppc64.h.inc
+++ /dev/null
@@ -1 +0,0 @@
-#define LLVM_LIBC_CACHELINE_SIZE 128
diff --git a/src/string/memory_utils/cacheline_size_x86.h.inc b/src/string/memory_utils/cacheline_size_x86.h.inc
deleted file mode 100644
index 29da174..0000000
--- a/src/string/memory_utils/cacheline_size_x86.h.inc
+++ /dev/null
@@ -1 +0,0 @@
-#define LLVM_LIBC_CACHELINE_SIZE 64
diff --git a/src/string/memory_utils/cacheline_size_x86_64.h.inc b/src/string/memory_utils/cacheline_size_x86_64.h.inc
deleted file mode 100644
index 29da174..0000000
--- a/src/string/memory_utils/cacheline_size_x86_64.h.inc
+++ /dev/null
@@ -1 +0,0 @@
-#define LLVM_LIBC_CACHELINE_SIZE 64
diff --git a/src/string/memory_utils/utils.h b/src/string/memory_utils/utils.h
index c2472c2..d6047e1 100644
--- a/src/string/memory_utils/utils.h
+++ b/src/string/memory_utils/utils.h
@@ -6,10 +6,26 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIBC_SRC_MEMORY_UTILS_H
-#define LLVM_LIBC_SRC_MEMORY_UTILS_H
+#ifndef LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H
+#define LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H
-#include "src/string/memory_utils/cacheline_size.h"
+// Cache line sizes for ARM: These values are not strictly correct since
+// cache line sizes depend on implementations, not architectures. There
+// are even implementations with cache line sizes configurable at boot
+// time.
+#if defined(__aarch64__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#elif defined(__ARM_ARCH_5T__)
+#define LLVM_LIBC_CACHELINE_SIZE 32
+#elif defined(__ARM_ARCH_7A__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#elif defined(__PPC64__)
+#define LLVM_LIBC_CACHELINE_SIZE 128
+#elif defined(__i386__) || defined(__x86_64__)
+#define LLVM_LIBC_CACHELINE_SIZE 64
+#else
+#error "Unsupported platform for memory functions."
+#endif
#include <stddef.h> // size_t
#include <stdint.h> // intptr_t / uintptr_t
@@ -66,4 +82,4 @@
} // namespace __llvm_libc
-#endif // LLVM_LIBC_SRC_MEMORY_UTILS_H
+#endif // LLVM_LIBC_SRC_MEMORY_UTILS_UTILS_H
