| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 |
| |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 |
| |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 |
| |
| // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // expected-no-diagnostics |
| #ifndef ARRAY |
| #ifndef HEADER |
| #define HEADER |
| |
| enum omp_allocator_handle_t { |
| omp_null_allocator = 0, |
| omp_default_mem_alloc = 1, |
| omp_large_cap_mem_alloc = 2, |
| omp_const_mem_alloc = 3, |
| omp_high_bw_mem_alloc = 4, |
| omp_low_lat_mem_alloc = 5, |
| omp_cgroup_mem_alloc = 6, |
| omp_pteam_mem_alloc = 7, |
| omp_thread_mem_alloc = 8, |
| KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__ |
| }; |
| |
| struct St { |
| int a, b; |
| St() : a(0), b(0) {} |
| St(const St &st) : a(st.a + st.b), b(0) {} |
| ~St() {} |
| }; |
| |
| volatile int g __attribute__((aligned(128))) = 1212; |
| |
| struct SS { |
| int a; |
| int b : 4; |
| int &c; |
| int e[4]; |
| SS(int &d) : a(0), b(0), c(d) { |
| #pragma omp parallel firstprivate(a, b, c, e) |
| #ifdef LAMBDA |
| [&]() { |
| ++this->a, --b, (this)->c /= 1; |
| #pragma omp parallel firstprivate(a, b, c) |
| ++(this)->a, --b, this->c /= 1; |
| }(); |
| #elif defined(BLOCKS) |
| ^{ |
| ++a; |
| --this->b; |
| (this)->c /= 1; |
| #pragma omp parallel firstprivate(a, b, c) |
| ++(this)->a, --b, this->c /= 1; |
| }(); |
| #else |
| ++this->a, --b, c /= 1, e[2] = 1111; |
| #endif |
| } |
| }; |
| |
| template<typename T> |
| struct SST { |
| T a; |
| SST() : a(T()) { |
| #pragma omp parallel firstprivate(a) |
| #ifdef LAMBDA |
| [&]() { |
| [&]() { |
| ++this->a; |
| #pragma omp parallel firstprivate(a) |
| ++(this)->a; |
| }(); |
| }(); |
| #elif defined(BLOCKS) |
| ^{ |
| ^{ |
| ++a; |
| #pragma omp parallel firstprivate(a) |
| ++(this)->a; |
| }(); |
| }(); |
| #else |
| ++(this)->a; |
| #endif |
| } |
| }; |
| |
| template <class T> |
| struct S { |
| T f; |
| S(T a) : f(a + g) {} |
| S() : f(g) {} |
| S(const S &s, St t = St()) : f(s.f + t.a) {} |
| operator T() { return T(); } |
| ~S() {} |
| }; |
| |
| |
| template <typename T> |
| T tmain() { |
| S<T> test; |
| SST<T> sst; |
| T t_var __attribute__((aligned(128))) = T(); |
| T vec[] __attribute__((aligned(128))) = {1, 2}; |
| S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; |
| S<T> var __attribute__((aligned(128))) (3); |
| #pragma omp parallel firstprivate(t_var, vec, s_arr, var) |
| { |
| vec[0] = t_var; |
| s_arr[0] = var; |
| } |
| #pragma omp parallel firstprivate(t_var) |
| {} |
| return T(); |
| } |
| |
| int main() { |
| static int sivar; |
| SS ss(sivar); |
| #ifdef LAMBDA |
| [&]() { |
| #pragma omp parallel firstprivate(g, sivar) |
| { |
| |
| |
| |
| g = 1; |
| sivar = 2; |
| [&]() { |
| g = 2; |
| sivar = 4; |
| }(); |
| } |
| }(); |
| return 0; |
| #elif defined(BLOCKS) |
| ^{ |
| #pragma omp parallel firstprivate(g, sivar) |
| { |
| g = 1; |
| sivar = 2; |
| ^{ |
| g = 2; |
| sivar = 4; |
| }(); |
| } |
| }(); |
| return 0; |
| |
| |
| #else |
| S<float> test; |
| int t_var = 0; |
| int vec[] = {1, 2}; |
| S<float> s_arr[] = {1, 2}; |
| S<float> var(3); |
| #pragma omp parallel firstprivate(t_var, vec, s_arr, var, sivar) |
| { |
| vec[0] = t_var; |
| s_arr[0] = var; |
| sivar = 2; |
| } |
| const int a = 0; |
| #pragma omp parallel allocate(omp_default_mem_alloc: t_var) firstprivate(t_var, a) |
| { t_var = a; } |
| return tmain<int>(); |
| #endif |
| } |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| #endif |
| #else |
| |
| enum omp_allocator_handle_t { |
| omp_null_allocator = 0, |
| omp_default_mem_alloc = 1, |
| omp_large_cap_mem_alloc = 2, |
| omp_const_mem_alloc = 3, |
| omp_high_bw_mem_alloc = 4, |
| omp_low_lat_mem_alloc = 5, |
| omp_cgroup_mem_alloc = 6, |
| omp_pteam_mem_alloc = 7, |
| omp_thread_mem_alloc = 8, |
| KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__ |
| }; |
| |
| struct St { |
| int a, b; |
| St() : a(0), b(0) {} |
| St(const St &) { } |
| ~St() {} |
| void St_func(St s[2], int n, long double vla1[n]) { |
| double vla2[n][n] __attribute__((aligned(128))); |
| a = b; |
| #pragma omp parallel allocate(omp_thread_mem_alloc:vla2) firstprivate(s, vla1, vla2) |
| vla1[b] = vla2[1][n - 1] = a = b; |
| } |
| }; |
| |
| void array_func(float a[3], St s[2], int n, long double vla1[n]) { |
| double vla2[n][n] __attribute__((aligned(128))); |
| #pragma omp parallel firstprivate(a, s, vla1, vla2) |
| s[0].St_func(s, n, vla1); |
| ; |
| } |
| |
| #endif |
| |
| // CHECK1-LABEL: define {{[^@]+}}@main |
| // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 |
| // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 |
| // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) |
| // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP3]]) |
| // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i32 [[TMP5]]) |
| // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() |
| // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done2: |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP7]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 |
| // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done3: |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) |
| // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) |
| // CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done8: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1 |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i32 4, ptr inttoptr (i32 1 to ptr)) |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i32 1 to ptr)) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK1-SAME: () #[[ATTR1]] comdat { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 |
| // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 |
| // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 |
| // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 |
| // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 |
| // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]]) |
| // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 128 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) |
| // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) |
| // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 |
| // CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128 |
| // CHECK1-NEXT: store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i32 [[TMP3]]) |
| // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done2: |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP5]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A2:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[C7:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[E:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 4 |
| // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 4 |
| // CHECK1-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK1-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK1-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK1-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK1-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK1-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK1-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C7]], align 4 |
| // CHECK1-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[E9]], ptr [[E]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 |
| // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK1-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 4 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false) |
| // CHECK1-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 |
| // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP5]], -1 |
| // CHECK1-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP7]], 1 |
| // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i32 0, i32 2 |
| // CHECK1-NEXT: store i32 1111, ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float |
| // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float |
| // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] |
| // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float |
| // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] |
| // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 |
| // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 |
| // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 |
| // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false) |
| // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK1: omp.arraycpy.body: |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] |
| // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK1: omp.arraycpy.done3: |
| // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) |
| // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) |
| // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 |
| // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2 |
| // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK1: arraydestroy.body: |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] |
| // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK1: arraydestroy.done8: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.2 |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A2:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i32 [[TMP2]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined |
| // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 |
| // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@main |
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK3-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) |
| // CHECK3-NEXT: ret i32 0 |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A2:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[C7:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[E:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 4 |
| // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[A3]], ptr [[A2]], align 4 |
| // CHECK3-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK3-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK3-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK3-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK3-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK3-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK3-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[C7]], align 4 |
| // CHECK3-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[E9]], ptr [[E]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 |
| // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK3-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4 |
| // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false) |
| // CHECK3-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[B_ADDR]], ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 4 dereferenceable(16) [[REF_TMP]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv |
| // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 |
| // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 |
| // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 |
| // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[C_CASTED]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i32 [[TMP14]], i32 [[TMP18]], i32 [[TMP22]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined |
| // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK3-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 |
| // CHECK3-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 |
| // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@main |
| // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 |
| // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 4 |
| // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK4-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 4 |
| // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4 |
| // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 4 |
| // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4 |
| // CHECK4-NEXT: call void [[TMP2]](ptr [[BLOCK]]) |
| // CHECK4-NEXT: ret i32 0 |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK4-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke |
| // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[G_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK4-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK4-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 |
| // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined |
| // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, align 128 |
| // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 1, ptr [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128 |
| // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4 |
| // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 8 |
| // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 4 |
| // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 16 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK4-NEXT: call void [[TMP3]](ptr [[BLOCK]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke |
| // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 |
| // CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[A2:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[C7:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[E:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 4 |
| // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 4 |
| // CHECK4-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK4-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK4-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK4-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK4-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK4-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK4-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4 |
| // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C7]], align 4 |
| // CHECK4-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr [[E9]], ptr [[E]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 4 |
| // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 |
| // CHECK4-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, align 4 |
| // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 4 |
| // CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4 |
| // CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false) |
| // CHECK4-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 4 |
| // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 4 |
| // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4 |
| // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 4 |
| // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK4-NEXT: store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 6 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK4-NEXT: store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 7 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 8 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK4-NEXT: store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 |
| // CHECK4-NEXT: call void [[TMP7]](ptr [[BLOCK]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 |
| // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 |
| // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 |
| // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 4 |
| // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 |
| // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 |
| // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 4 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP11]], ptr [[C_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[C_CASTED]], align 4 |
| // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i32 [[TMP7]], i32 [[TMP9]], i32 [[TMP12]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined |
| // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR3]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 4 |
| // CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 |
| // CHECK4-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 |
| // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@main |
| // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK9-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP3]]) |
| // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP5]]) |
| // CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() |
| // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done2: |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP7]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done3: |
| // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) |
| // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) |
| // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 |
| // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 |
| // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) |
| // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done8: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined.1 |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i64 4, ptr inttoptr (i64 1 to ptr)) |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 4 |
| // CHECK9-NEXT: store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i64 1 to ptr)) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK9-SAME: () #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]]) |
| // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 128 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 |
| // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128 |
| // CHECK9-NEXT: store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i64 [[TMP3]]) |
| // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done2: |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP5]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A2:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[C7:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[E:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 0, ptr [[A]], align 8 |
| // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK9-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 |
| // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store ptr [[A3]], ptr [[A2]], align 8 |
| // CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK9-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 |
| // CHECK9-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[E9]], ptr [[E]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 |
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[E3:%.*]] = alloca [4 x i32], align 16 |
| // CHECK9-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false) |
| // CHECK9-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 |
| // CHECK9-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP5]], -1 |
| // CHECK9-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP7]], 1 |
| // CHECK9-NEXT: store i32 [[DIV]], ptr [[TMP6]], align 4 |
| // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i64 0, i64 2 |
| // CHECK9-NEXT: store i32 1111, ptr [[ARRAYIDX]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float |
| // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float |
| // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] |
| // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK9-NEXT: store i32 0, ptr [[B]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float |
| // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] |
| // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 |
| // CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 |
| // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 |
| // CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 |
| // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) |
| // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) |
| // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done3: |
| // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) |
| // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) |
| // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 |
| // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 |
| // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done8: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.2 |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A2:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 |
| // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store ptr [[A3]], ptr [[A2]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined |
| // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK9-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] |
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] |
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@main |
| // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 |
| // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK11-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 |
| // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]]) |
| // CHECK11-NEXT: ret i32 0 |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK11-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[A2:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[C7:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[E:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 0, ptr [[A]], align 8 |
| // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK11-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 |
| // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store ptr [[A3]], ptr [[A2]], align 8 |
| // CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK11-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK11-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK11-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 |
| // CHECK11-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 |
| // CHECK11-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[E9]], ptr [[E]], align 8 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 8 |
| // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[E3:%.*]] = alloca [4 x i32], align 16 |
| // CHECK11-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 |
| // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK11-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 |
| // CHECK11-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false) |
| // CHECK11-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 8 |
| // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP3]], align 8 |
| // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK11-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8 |
| // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[B_ADDR]], ptr [[TMP6]], align 8 |
| // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK11-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 |
| // CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 8 dereferenceable(32) [[REF_TMP]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv |
| // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 |
| // CHECK11-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 |
| // CHECK11-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 |
| // CHECK11-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8 |
| // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined |
| // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK11-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK11-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK11-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 |
| // CHECK11-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 |
| // CHECK11-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@main |
| // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 |
| // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8 |
| // CHECK12-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK12-NEXT: call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) |
| // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK12-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 |
| // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK12-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 |
| // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK12-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8 |
| // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK12-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK12-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8 |
| // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK12-NEXT: call void [[TMP2]](ptr [[BLOCK]]) |
| // CHECK12-NEXT: ret i32 0 |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi |
| // CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK12-NEXT: call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke |
| // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 |
| // CHECK12-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 |
| // CHECK12-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 |
| // CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined |
| // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 128 |
| // CHECK12-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 |
| // CHECK12-NEXT: store i32 1, ptr [[G_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK12-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128 |
| // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK12-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 |
| // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK12-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 16 |
| // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK12-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4 |
| // CHECK12-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 32 |
| // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK12-NEXT: call void [[TMP3]](ptr [[BLOCK]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke |
| // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK12-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 |
| // CHECK12-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 32 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi |
| // CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[A2:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[B4:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[C7:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[E:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: store i32 0, ptr [[A]], align 8 |
| // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4 |
| // CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 |
| // CHECK12-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 |
| // CHECK12-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 |
| // CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 |
| // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: store ptr [[A3]], ptr [[A2]], align 8 |
| // CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK12-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4 |
| // CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 |
| // CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 |
| // CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 |
| // CHECK12-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 |
| // CHECK12-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 |
| // CHECK12-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 |
| // CHECK12-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 |
| // CHECK12-NEXT: store ptr [[E9]], ptr [[E]], align 8 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 |
| // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[E]], align 8 |
| // CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined |
| // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[E3:%.*]] = alloca [4 x i32], align 16 |
| // CHECK12-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, align 8 |
| // CHECK12-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[E]], ptr [[E_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK12-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 |
| // CHECK12-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8 |
| // CHECK12-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false) |
| // CHECK12-NEXT: store ptr [[E3]], ptr [[_TMP4]], align 8 |
| // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 |
| // CHECK12-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 |
| // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 |
| // CHECK12-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 |
| // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 |
| // CHECK12-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 |
| // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8 |
| // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 |
| // CHECK12-NEXT: store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 |
| // CHECK12-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK12-NEXT: store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK12-NEXT: store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 8 |
| // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 |
| // CHECK12-NEXT: call void [[TMP7]](ptr [[BLOCK]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2 |
| // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 |
| // CHECK12-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 |
| // CHECK12-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 |
| // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 |
| // CHECK12-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 |
| // CHECK12-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 8 |
| // CHECK12-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8 |
| // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 |
| // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8 |
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP11]], ptr [[C_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP12:%.*]] = load i64, ptr [[C_CASTED]], align 8 |
| // CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined |
| // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK12-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK12-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK12-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 |
| // CHECK12-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 |
| // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 |
| // CHECK12-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 |
| // CHECK12-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 |
| // CHECK12-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe |
| // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 |
| // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() |
| // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] |
| // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 |
| // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 |
| // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 8, ptr @_Z10array_funcPfP2StiPe.omp_outlined, ptr [[TMP8]], ptr [[N_ADDR]], i64 [[TMP1]], ptr [[TMP9]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]]) |
| // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe.omp_outlined |
| // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 |
| // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0() |
| // CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] |
| // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 |
| // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 |
| // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] |
| // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 |
| // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false) |
| // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]]) |
| // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe |
| // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] align 2 { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 |
| // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() |
| // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] |
| // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 |
| // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 |
| // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 |
| // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 |
| // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A]], align 4 |
| // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 8, ptr @_ZN2St7St_funcEPS_iPe.omp_outlined, i64 [[TMP1]], ptr [[TMP9]], ptr [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[N_ADDR]], ptr [[TMP10]]) |
| // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 |
| // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe.omp_outlined |
| // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 |
| // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 |
| // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] |
| // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8 |
| // CHECK17-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127 |
| // CHECK17-NEXT: [[TMP9:%.*]] = udiv i64 [[TMP8]], 128 |
| // CHECK17-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128 |
| // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 |
| // CHECK17-NEXT: [[DOTVLA2__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], ptr inttoptr (i64 8 to ptr)) |
| // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] |
| // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 |
| // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[DOTVLA2__VOID_ADDR]], ptr align 128 [[TMP4]], i64 [[TMP14]], i1 false) |
| // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 |
| // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0 |
| // CHECK17-NEXT: store i32 [[TMP15]], ptr [[A]], align 4 |
| // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP15]] to double |
| // CHECK17-NEXT: [[TMP16:%.*]] = mul nsw i64 1, [[TMP3]] |
| // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[DOTVLA2__VOID_ADDR]], i64 [[TMP16]] |
| // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4 |
| // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP17]], 1 |
| // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 [[IDXPROM]] |
| // CHECK17-NEXT: store double [[CONV]], ptr [[ARRAYIDX7]], align 8 |
| // CHECK17-NEXT: [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80 |
| // CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 |
| // CHECK17-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[B9]], align 4 |
| // CHECK17-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP18]], i64 [[IDXPROM10]] |
| // CHECK17-NEXT: store x86_fp80 [[CONV8]], ptr [[ARRAYIDX11]], align 16 |
| // CHECK17-NEXT: call void @__kmpc_free(i32 [[TMP12]], ptr [[DOTVLA2__VOID_ADDR]], ptr inttoptr (i64 8 to ptr)) |
| // CHECK17-NEXT: ret void |
| // |
