| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // Test host codegen. |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -verify -fopenmp-version=45 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 |
| // Test host codegen. |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK17 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK17 |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK19 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK19 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| |
| void without_schedule_clause(float *a, float *b, float *c, float *d) { |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute |
| for (int i = 33; i < 32000000; i += 7) { |
| a[i] = b[i] * c[i] * d[i]; |
| } |
| } |
| |
| // ... loop body ... |
| |
| |
| void static_not_chunked(float *a, float *b, float *c, float *d) { |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute dist_schedule(static) |
| for (int i = 32000000; i > 33; i += -7) { |
| a[i] = b[i] * c[i] * d[i]; |
| } |
| } |
| |
| // ... loop body ... |
| |
| |
| void static_chunked(float *a, float *b, float *c, float *d) { |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute dist_schedule(static, 5) |
| for (unsigned i = 131071; i <= 2147483647; i += 127) { |
| a[i] = b[i] * c[i] * d[i]; |
| } |
| } |
| |
| // ... loop body ... |
| |
| void test_precond() { |
| char a = 0; |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute |
| for(char i = a; i < 10; ++i); |
| } |
| |
| // a is passed as a parameter to the outlined functions |
| // ..many loads of %0.. |
| |
| // no templates for now, as these require special handling in target regions and/or declare target |
| |
| |
| template <typename T> |
| T ftemplate() { |
| short aa = 0; |
| |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute dist_schedule(static, aa) |
| for (int i = 0; i < 100; i++) { |
| } |
| return T(); |
| } |
| |
| int fint(void) { return ftemplate<int>(); } |
| |
| #endif |
| // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 8 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 |
| // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 4571424, ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] |
| // CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] |
| // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 |
| // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] |
| // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 |
| // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] |
| // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] |
| // CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 |
| // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 4571424, ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] |
| // CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] |
| // CHECK1-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] |
| // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 |
| // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] |
| // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 |
| // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] |
| // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] |
| // CHECK1-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 8 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8 |
| // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 16908289, ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 |
| // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK1: omp.dispatch.cond: |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK1: omp.dispatch.body: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] |
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 |
| // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] |
| // CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] |
| // CHECK1-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] |
| // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] |
| // CHECK1-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] |
| // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] |
| // CHECK1-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 |
| // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK1: omp.dispatch.inc: |
| // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] |
| // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] |
| // CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK1: omp.dispatch.end: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z12test_precondv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: store i8 0, ptr [[A]], align 1 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 |
| // CHECK1-NEXT: store i8 [[TMP0]], ptr [[A_CASTED]], align 1 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[A]], align 1 |
| // CHECK1-NEXT: store i8 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 |
| // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[ADD4]] to i64 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP11]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 1, ptr [[TMP12]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP23]], align 4 |
| // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i64 [[TMP1]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 |
| // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I5:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i8, ptr [[TMP0]], align 1 |
| // CHECK1-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: store i8 [[TMP3]], ptr [[I]], align 1 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK1: omp.precond.then: |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] |
| // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] |
| // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] |
| // CHECK1-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 |
| // CHECK1-NEXT: store i8 [[CONV10]], ptr [[I5]], align 1 |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 |
| // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) |
| // CHECK1-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK1: omp.precond.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z4fintv |
| // CHECK1-SAME: () #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_v() |
| // CHECK1-NEXT: ret i32 [[CALL]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v |
| // CHECK1-SAME: () #[[ATTR0]] comdat { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 |
| // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 |
| // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK1-NEXT: store i32 3, ptr [[TMP7]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK1-NEXT: store i32 1, ptr [[TMP8]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK1-NEXT: store i64 100, ptr [[TMP15]], align 8 |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i64 [[TMP1]]) #[[ATTR2]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: ret i32 0 |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 |
| // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 |
| // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK1: omp.dispatch.cond: |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK1: omp.dispatch.body: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] |
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] |
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 |
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK1: omp.dispatch.inc: |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] |
| // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] |
| // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK1: omp.dispatch.end: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP22]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 |
| // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 4571424, ptr [[TMP26]], align 8 |
| // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] |
| // CHECK3-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] |
| // CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 |
| // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] |
| // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 |
| // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] |
| // CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] |
| // CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 |
| // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 4571424, ptr [[TMP26]], align 8 |
| // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] |
| // CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] |
| // CHECK3-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] |
| // CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 |
| // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] |
| // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 |
| // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] |
| // CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] |
| // CHECK3-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 4, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP22]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4 |
| // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 16908289, ptr [[TMP26]], align 8 |
| // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP27]], align 8 |
| // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP30]], align 4 |
| // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 |
| // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80(ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 |
| // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK3: omp.dispatch.cond: |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK3: omp.dispatch.body: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] |
| // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 |
| // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] |
| // CHECK3-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] |
| // CHECK3-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] |
| // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] |
| // CHECK3-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] |
| // CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] |
| // CHECK3-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 |
| // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK3: omp.dispatch.inc: |
| // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] |
| // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] |
| // CHECK3-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK3: omp.dispatch.end: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z12test_precondv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: store i8 0, ptr [[A]], align 1 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 |
| // CHECK3-NEXT: store i8 [[TMP0]], ptr [[A_CASTED]], align 1 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[A]], align 1 |
| // CHECK3-NEXT: store i8 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP8]] to i32 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 |
| // CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[ADD4]] to i64 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 1, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP15]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 [[TMP10]], ptr [[TMP19]], align 8 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP20]], align 8 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP22]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92(i32 [[TMP1]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 |
| // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I5:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i8, ptr [[TMP0]], align 1 |
| // CHECK3-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: store i8 [[TMP3]], ptr [[I]], align 1 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK3: omp.precond.then: |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] |
| // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] |
| // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] |
| // CHECK3-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 |
| // CHECK3-NEXT: store i8 [[CONV10]], ptr [[I5]], align 1 |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 |
| // CHECK3-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) |
| // CHECK3-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK3: omp.precond.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z4fintv |
| // CHECK3-SAME: () #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_v() |
| // CHECK3-NEXT: ret i32 [[CALL]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_v |
| // CHECK3-SAME: () #[[ATTR0]] comdat { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 |
| // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA]], align 2 |
| // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i32 3, ptr [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i32 1, ptr [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP10]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP12]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK3-NEXT: store i64 100, ptr [[TMP15]], align 8 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK3-NEXT: store i64 0, ptr [[TMP16]], align 8 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108(i32 [[TMP1]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: ret i32 0 |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 |
| // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 |
| // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK3: omp.dispatch.cond: |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK3: omp.dispatch.body: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 |
| // CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK3: omp.dispatch.inc: |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] |
| // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] |
| // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK3: omp.dispatch.end: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 |
| // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined |
| // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK17: cond.true: |
| // CHECK17-NEXT: br label [[COND_END:%.*]] |
| // CHECK17: cond.false: |
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[COND_END]] |
| // CHECK17: cond.end: |
| // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK17: omp.inner.for.cond: |
| // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK17: omp.inner.for.body: |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] |
| // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] |
| // CHECK17-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] |
| // CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 |
| // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 |
| // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] |
| // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 |
| // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] |
| // CHECK17-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] |
| // CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 |
| // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK17: omp.body.continue: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK17: omp.inner.for.inc: |
| // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK17-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK17: omp.inner.for.end: |
| // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK17: omp.loop.exit: |
| // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 |
| // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined |
| // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK17: cond.true: |
| // CHECK17-NEXT: br label [[COND_END:%.*]] |
| // CHECK17: cond.false: |
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[COND_END]] |
| // CHECK17: cond.end: |
| // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK17: omp.inner.for.cond: |
| // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK17: omp.inner.for.body: |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] |
| // CHECK17-NEXT: store i32 [[SUB]], ptr [[I]], align 4 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]] |
| // CHECK17-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8 |
| // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]] |
| // CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 |
| // CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8 |
| // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]] |
| // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 |
| // CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] |
| // CHECK17-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| // CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]] |
| // CHECK17-NEXT: store float [[MUL7]], ptr [[ARRAYIDX9]], align 4 |
| // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK17: omp.body.continue: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK17: omp.inner.for.inc: |
| // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK17: omp.inner.for.end: |
| // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK17: omp.loop.exit: |
| // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 |
| // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined |
| // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK17: omp.dispatch.cond: |
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 |
| // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK17: cond.true: |
| // CHECK17-NEXT: br label [[COND_END:%.*]] |
| // CHECK17: cond.false: |
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[COND_END]] |
| // CHECK17: cond.end: |
| // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] |
| // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK17: omp.dispatch.body: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK17: omp.inner.for.cond: |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] |
| // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] |
| // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK17: omp.inner.for.body: |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 |
| // CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] |
| // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]] |
| // CHECK17-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]] |
| // CHECK17-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] |
| // CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]] |
| // CHECK17-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] |
| // CHECK17-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 |
| // CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]] |
| // CHECK17-NEXT: store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK17: omp.body.continue: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK17: omp.inner.for.inc: |
| // CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 |
| // CHECK17-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] |
| // CHECK17: omp.inner.for.end: |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK17: omp.dispatch.inc: |
| // CHECK17-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] |
| // CHECK17-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] |
| // CHECK17-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK17: omp.dispatch.end: |
| // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 |
| // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined |
| // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I5:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i8, ptr [[TMP0]], align 1 |
| // CHECK17-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 |
| // CHECK17-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK17-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK17-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK17-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK17-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK17-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: store i8 [[TMP3]], ptr [[I]], align 1 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 |
| // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK17: omp.precond.then: |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] |
| // CHECK17-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK17: cond.true: |
| // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK17-NEXT: br label [[COND_END:%.*]] |
| // CHECK17: cond.false: |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[COND_END]] |
| // CHECK17: cond.end: |
| // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] |
| // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK17: omp.inner.for.cond: |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] |
| // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK17: omp.inner.for.body: |
| // CHECK17-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 |
| // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] |
| // CHECK17-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 |
| // CHECK17-NEXT: store i8 [[CONV10]], ptr [[I5]], align 1 |
| // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK17: omp.body.continue: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK17: omp.inner.for.inc: |
| // CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 |
| // CHECK17-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK17: omp.inner.for.end: |
| // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK17: omp.loop.exit: |
| // CHECK17-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) |
| // CHECK17-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK17: omp.precond.end: |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 |
| // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 |
| // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined |
| // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 |
| // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK17: omp.dispatch.cond: |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 |
| // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK17: cond.true: |
| // CHECK17-NEXT: br label [[COND_END:%.*]] |
| // CHECK17: cond.false: |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[COND_END]] |
| // CHECK17: cond.end: |
| // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] |
| // CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] |
| // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK17: omp.dispatch.body: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK17: omp.inner.for.cond: |
| // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] |
| // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK17: omp.inner.for.body: |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK17: omp.body.continue: |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK17: omp.inner.for.inc: |
| // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 |
| // CHECK17-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] |
| // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] |
| // CHECK17: omp.inner.for.end: |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK17: omp.dispatch.inc: |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] |
| // CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] |
| // CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK17: omp.dispatch.end: |
| // CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56 |
| // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined |
| // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK19: cond.true: |
| // CHECK19-NEXT: br label [[COND_END:%.*]] |
| // CHECK19: cond.false: |
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[COND_END]] |
| // CHECK19: cond.end: |
| // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK19: omp.inner.for.cond: |
| // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK19: omp.inner.for.body: |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] |
| // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 |
| // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] |
| // CHECK19-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] |
| // CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 |
| // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 |
| // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] |
| // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 |
| // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] |
| // CHECK19-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 |
| // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] |
| // CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 |
| // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK19: omp.body.continue: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK19: omp.inner.for.inc: |
| // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK19-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK19: omp.inner.for.end: |
| // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK19: omp.loop.exit: |
| // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68 |
| // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined |
| // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 4571423, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 |
| // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK19: cond.true: |
| // CHECK19-NEXT: br label [[COND_END:%.*]] |
| // CHECK19: cond.false: |
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[COND_END]] |
| // CHECK19: cond.end: |
| // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK19: omp.inner.for.cond: |
| // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK19: omp.inner.for.body: |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 |
| // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] |
| // CHECK19-NEXT: store i32 [[SUB]], ptr [[I]], align 4 |
| // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 4 |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 [[TMP13]] |
| // CHECK19-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4 |
| // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 4 |
| // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i32 [[TMP16]] |
| // CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 |
| // CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]] |
| // CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 4 |
| // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i32 [[TMP19]] |
| // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 |
| // CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]] |
| // CHECK19-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 4 |
| // CHECK19-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 |
| // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i32 [[TMP22]] |
| // CHECK19-NEXT: store float [[MUL5]], ptr [[ARRAYIDX6]], align 4 |
| // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK19: omp.body.continue: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK19: omp.inner.for.inc: |
| // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 |
| // CHECK19-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK19: omp.inner.for.end: |
| // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK19: omp.loop.exit: |
| // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80 |
| // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined |
| // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK19: omp.dispatch.cond: |
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 |
| // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK19: cond.true: |
| // CHECK19-NEXT: br label [[COND_END:%.*]] |
| // CHECK19: cond.false: |
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[COND_END]] |
| // CHECK19: cond.end: |
| // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] |
| // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] |
| // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK19: omp.dispatch.body: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK19: omp.inner.for.cond: |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] |
| // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] |
| // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK19: omp.inner.for.body: |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 |
| // CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] |
| // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 [[TMP15]] |
| // CHECK19-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 [[TMP18]] |
| // CHECK19-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]] |
| // CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i32 [[TMP21]] |
| // CHECK19-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX5]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]] |
| // CHECK19-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i32 [[TMP24]] |
| // CHECK19-NEXT: store float [[MUL6]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK19: omp.body.continue: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK19: omp.inner.for.inc: |
| // CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1 |
| // CHECK19-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] |
| // CHECK19: omp.inner.for.end: |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK19: omp.dispatch.inc: |
| // CHECK19-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]] |
| // CHECK19-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: [[ADD10:%.*]] = add i32 [[TMP28]], [[TMP29]] |
| // CHECK19-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK19: omp.dispatch.end: |
| // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92 |
| // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A_ADDR]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined |
| // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 1 dereferenceable(1) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I5:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i8, ptr [[TMP0]], align 1 |
| // CHECK19-NEXT: store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[CONV:%.*]] = sext i8 [[TMP2]] to i32 |
| // CHECK19-NEXT: [[SUB:%.*]] = sub i32 10, [[CONV]] |
| // CHECK19-NEXT: [[SUB2:%.*]] = sub i32 [[SUB]], 1 |
| // CHECK19-NEXT: [[ADD:%.*]] = add i32 [[SUB2]], 1 |
| // CHECK19-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 |
| // CHECK19-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK19-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: store i8 [[TMP3]], ptr [[I]], align 1 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[CONV4:%.*]] = sext i8 [[TMP4]] to i32 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp slt i32 [[CONV4]], 10 |
| // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK19: omp.precond.then: |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK19-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]] |
| // CHECK19-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK19: cond.true: |
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK19-NEXT: br label [[COND_END:%.*]] |
| // CHECK19: cond.false: |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[COND_END]] |
| // CHECK19: cond.end: |
| // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] |
| // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK19: omp.inner.for.cond: |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] |
| // CHECK19-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK19: omp.inner.for.body: |
| // CHECK19-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[CONV8:%.*]] = sext i8 [[TMP15]] to i32 |
| // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK19-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[MUL]] |
| // CHECK19-NEXT: [[CONV10:%.*]] = trunc i32 [[ADD9]] to i8 |
| // CHECK19-NEXT: store i8 [[CONV10]], ptr [[I5]], align 1 |
| // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK19: omp.body.continue: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK19: omp.inner.for.inc: |
| // CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP17]], 1 |
| // CHECK19-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK19: omp.inner.for.end: |
| // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK19: omp.loop.exit: |
| // CHECK19-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) |
| // CHECK19-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK19: omp.precond.end: |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108 |
| // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 |
| // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA_ADDR]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined |
| // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2 |
| // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[CONV]]) |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] |
| // CHECK19: omp.dispatch.cond: |
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 |
| // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK19: cond.true: |
| // CHECK19-NEXT: br label [[COND_END:%.*]] |
| // CHECK19: cond.false: |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[COND_END]] |
| // CHECK19: cond.end: |
| // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] |
| // CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 |
| // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] |
| // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] |
| // CHECK19: omp.dispatch.body: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK19: omp.inner.for.cond: |
| // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] |
| // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] |
| // CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] |
| // CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK19: omp.inner.for.body: |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] |
| // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] |
| // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK19: omp.body.continue: |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK19: omp.inner.for.inc: |
| // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] |
| // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 |
| // CHECK19-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] |
| // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] |
| // CHECK19: omp.inner.for.end: |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] |
| // CHECK19: omp.dispatch.inc: |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] |
| // CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4 |
| // CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] |
| // CHECK19-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] |
| // CHECK19: omp.dispatch.end: |
| // CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) |
| // CHECK19-NEXT: ret void |
| // |
