| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature |
| // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s |
| |
| // REQUIRES: aarch64-registered-target || arm-registered-target |
| |
| #include <arm_neon.h> |
| |
| // CHECK-LABEL: define {{[^@]+}}@test_vmaxnm_f32 |
| // CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <8 x i8> |
| // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <8 x i8> |
| // CHECK-NEXT: [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> [[A]], <2 x float> [[B]]) |
| // CHECK-NEXT: [[VMAXNM_V3_I:%.*]] = bitcast <2 x float> [[VMAXNM_V2_I]] to <8 x i8> |
| // CHECK-NEXT: ret <2 x float> [[VMAXNM_V2_I]] |
| // |
| float32x2_t test_vmaxnm_f32(float32x2_t a, float32x2_t b) { |
| return vmaxnm_f32(a, b); |
| } |
| |
| // CHECK-LABEL: define {{[^@]+}}@test_vmaxnmq_f32 |
| // CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <16 x i8> |
| // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <16 x i8> |
| // CHECK-NEXT: [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> [[A]], <4 x float> [[B]]) |
| // CHECK-NEXT: [[VMAXNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMAXNMQ_V2_I]] to <16 x i8> |
| // CHECK-NEXT: ret <4 x float> [[VMAXNMQ_V2_I]] |
| // |
| float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b) { |
| return vmaxnmq_f32(a, b); |
| } |
| |
| // CHECK-LABEL: define {{[^@]+}}@test_vminnm_f32 |
| // CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <8 x i8> |
| // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <8 x i8> |
| // CHECK-NEXT: [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> [[A]], <2 x float> [[B]]) |
| // CHECK-NEXT: [[VMINNM_V3_I:%.*]] = bitcast <2 x float> [[VMINNM_V2_I]] to <8 x i8> |
| // CHECK-NEXT: ret <2 x float> [[VMINNM_V2_I]] |
| // |
| float32x2_t test_vminnm_f32(float32x2_t a, float32x2_t b) { |
| return vminnm_f32(a, b); |
| } |
| |
| // CHECK-LABEL: define {{[^@]+}}@test_vminnmq_f32 |
| // CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR1]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <16 x i8> |
| // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <16 x i8> |
| // CHECK-NEXT: [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> [[A]], <4 x float> [[B]]) |
| // CHECK-NEXT: [[VMINNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMINNMQ_V2_I]] to <16 x i8> |
| // CHECK-NEXT: ret <4 x float> [[VMINNMQ_V2_I]] |
| // |
| float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b) { |
| return vminnmq_f32(a, b); |
| } |
| |
