| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ |
| // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ |
| // RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s |
| |
| // REQUIRES: aarch64-registered-target |
| |
| #include <arm_sve.h> |
| |
| #define N 512 |
| |
| typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N))); |
| |
| typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N))); |
| |
| typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N))); |
| typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N))); |
| |
| typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N))); |
| |
| // EQ |
| |
| // CHECK-LABEL: @eq_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t eq_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t eq_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t eq_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t eq_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t eq_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t eq_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t eq_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t eq_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t eq_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t eq_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t eq_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a == b; |
| } |
| |
| // CHECK-LABEL: @eq_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t eq_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a == b; |
| } |
| |
| // NEQ |
| |
| // CHECK-LABEL: @neq_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t neq_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t neq_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t neq_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t neq_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t neq_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t neq_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t neq_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t neq_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t neq_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp une <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t neq_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp une <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t neq_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a != b; |
| } |
| |
| // CHECK-LABEL: @neq_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp une <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t neq_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a != b; |
| } |
| |
| // LT |
| |
| // CHECK-LABEL: @lt_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t lt_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp slt <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t lt_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp slt <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t lt_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp slt <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t lt_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t lt_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ult <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t lt_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ult <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t lt_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ult <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t lt_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ult <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t lt_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t lt_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t lt_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a < b; |
| } |
| |
| // CHECK-LABEL: @lt_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp olt <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t lt_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a < b; |
| } |
| |
| // LEQ |
| |
| // CHECK-LABEL: @leq_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t leq_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sle <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t leq_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sle <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t leq_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sle <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t leq_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sle <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t leq_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ule <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t leq_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ule <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t leq_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ule <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t leq_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ule <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t leq_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t leq_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t leq_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a <= b; |
| } |
| |
| // CHECK-LABEL: @leq_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ole <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t leq_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a <= b; |
| } |
| |
| // GT |
| |
| // CHECK-LABEL: @gt_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t gt_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t gt_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t gt_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t gt_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t gt_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t gt_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t gt_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t gt_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp ugt <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t gt_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t gt_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t gt_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a > b; |
| } |
| |
| // CHECK-LABEL: @gt_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t gt_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a > b; |
| } |
| |
| // GEQ |
| |
| // CHECK-LABEL: @geq_bool( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0) |
| // CHECK-NEXT: [[B_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP1:%.*]] to <vscale x 2 x i8> |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[B_COERCE]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i8> [[CASTSCALABLESVE]] to <vscale x 16 x i1> |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]] |
| // |
| fixed_bool_t geq_bool(fixed_bool_t a, fixed_bool_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_i8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sge <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t geq_i8(fixed_int8_t a, fixed_int8_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_i16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sge <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t geq_i16(fixed_int16_t a, fixed_int16_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_i32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sge <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t geq_i32(fixed_int32_t a, fixed_int32_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_i64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp sge <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t geq_i64(fixed_int64_t a, fixed_int64_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp uge <64 x i8> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <64 x i1> [[CMP]] to <64 x i8> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[CASTSCALABLESVE]] |
| // |
| fixed_int8_t geq_u8(fixed_uint8_t a, fixed_uint8_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp uge <32 x i16> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t geq_u16(fixed_uint16_t a, fixed_uint16_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp uge <16 x i32> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t geq_u32(fixed_uint32_t a, fixed_uint32_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = icmp uge <8 x i64> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t geq_u64(fixed_uint64_t a, fixed_uint64_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16(<vscale x 8 x half> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CONV:%.*]] = fpext <32 x half> [[A]] to <32 x float> |
| // CHECK-NEXT: [[CONV2:%.*]] = fpext <32 x half> [[B]] to <32 x float> |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <32 x float> [[CONV]], [[CONV2]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <32 x i1> [[CMP]] to <32 x i32> |
| // CHECK-NEXT: [[CONV3:%.*]] = trunc <32 x i32> [[SEXT]] to <32 x i16> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[CONV3]], i64 0) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[CASTSCALABLESVE]] |
| // |
| fixed_int16_t geq_f16(fixed_float16_t a, fixed_float16_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32(<vscale x 4 x float> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <16 x float> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i32> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE]] |
| // |
| fixed_int32_t geq_f32(fixed_float32_t a, fixed_float32_t b) { |
| return a >= b; |
| } |
| |
| // CHECK-LABEL: @geq_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[A:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[A_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[B:%.*]] = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64(<vscale x 2 x double> [[B_COERCE:%.*]], i64 0) |
| // CHECK-NEXT: [[CMP:%.*]] = fcmp oge <8 x double> [[A]], [[B]] |
| // CHECK-NEXT: [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i64> |
| // CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[SEXT]], i64 0) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[CASTSCALABLESVE]] |
| // |
| fixed_int64_t geq_f64(fixed_float64_t a, fixed_float64_t b) { |
| return a >= b; |
| } |
