test/CodeGen/PowerPC/builtins-ecc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc-unknown-unknown \
// RUN:   -target-cpu future -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -flax-vector-conversions=none -triple powerpc64le-unknown-unknown \
// RUN:   -target-cpu future -emit-llvm %s -o - | FileCheck %s

// AI Generated.

vector unsigned char vuca, vucb, vucc;

// CHECK-LABEL: @test_xxmulmul(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmul(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 3)
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xxmulmul() {
  return __builtin_xxmulmul(vuca, vucb, 3);
}

// CHECK-LABEL: @test_xxmulmulhiadd(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 0, i32 1, i32 0)
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xxmulmulhiadd() {
  return __builtin_xxmulmulhiadd(vuca, vucb, 0, 1, 0);
}

// CHECK-LABEL: @test_xxmulmulloadd(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 1, i32 0)
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xxmulmulloadd() {
  return __builtin_xxmulmulloadd(vuca, vucb, 1, 0);
}

// CHECK-LABEL: @test_xxssumudm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxssumudm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 1)
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xxssumudm() {
  return __builtin_xxssumudm(vuca, vucb, 1);
}

// CHECK-LABEL: @test_xxssumudmc(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], i32 0)
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xxssumudmc() {
  return __builtin_xxssumudmc(vuca, vucb, 0);
}

// CHECK-LABEL: @test_xxssumudmcext(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = load <16 x i8>, ptr @vucc, align 16
// CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]], <16 x i8> [[TMP2]], i32 1)
// CHECK-NEXT:    ret <16 x i8> [[TMP3]]
//
vector unsigned char test_xxssumudmcext() {
  return __builtin_xxssumudmcext(vuca, vucb, vucc, 1);
}

// CHECK-LABEL: @test_xsaddadduqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsaddadduqm() {
  return __builtin_xsaddadduqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsaddaddsuqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsaddaddsuqm() {
  return __builtin_xsaddaddsuqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsaddsubuqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsaddsubuqm() {
  return __builtin_xsaddsubuqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsaddsubsuqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsaddsubsuqm() {
  return __builtin_xsaddsubsuqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsmerge2t1uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsmerge2t1uqm() {
  return __builtin_xsmerge2t1uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsmerge2t2uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsmerge2t2uqm() {
  return __builtin_xsmerge2t2uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsmerge2t3uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsmerge2t3uqm() {
  return __builtin_xsmerge2t3uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsmerge3t1uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsmerge3t1uqm() {
  return __builtin_xsmerge3t1uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase2t1uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase2t1uqm() {
  return __builtin_xsrebase2t1uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase2t2uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase2t2uqm() {
  return __builtin_xsrebase2t2uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase2t3uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase2t3uqm() {
  return __builtin_xsrebase2t3uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase2t4uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase2t4uqm() {
  return __builtin_xsrebase2t4uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase3t1uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase3t1uqm() {
  return __builtin_xsrebase3t1uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase3t2uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase3t2uqm() {
  return __builtin_xsrebase3t2uqm(vuca, vucb);
}

// CHECK-LABEL: @test_xsrebase3t3uqm(
// CHECK-NEXT:  entry:
// CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8> [[TMP0]], <16 x i8> [[TMP1]])
// CHECK-NEXT:    ret <16 x i8> [[TMP2]]
//
vector unsigned char test_xsrebase3t3uqm() {
  return __builtin_xsrebase3t3uqm(vuca, vucb);
}