| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 |
| |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 |
| |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| template <class T> |
| struct S { |
| T f; |
| S(T a) : f(a) {} |
| S() : f() {} |
| operator T() { return T(); } |
| ~S() {} |
| }; |
| |
| template <typename T> |
| T tmain() { |
| S<T> test; |
| T t_var = T(); |
| T vec[] = {1, 2}; |
| S<T> s_arr[] = {1, 2}; |
| S<T> &var = test; |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute simd lastprivate(t_var, vec, s_arr, s_arr, var, var) |
| for (int i = 0; i < 2; ++i) { |
| vec[i] = t_var; |
| s_arr[i] = var; |
| } |
| return T(); |
| } |
| |
| int main() { |
| static int svar; |
| volatile double g; |
| volatile double &g1 = g; |
| |
| #ifdef LAMBDA |
| [&]() { |
| static float sfvar; |
| |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute simd lastprivate(g, g1, svar, sfvar) |
| for (int i = 0; i < 2; ++i) { |
| // loop variables |
| |
| // init private variables |
| g = 1; |
| g1 = 1; |
| svar = 3; |
| sfvar = 4.0; |
| |
| // linear counter |
| |
| |
| |
| |
| [&]() { |
| g = 2; |
| g1 = 2; |
| svar = 4; |
| sfvar = 8.0; |
| |
| }(); |
| } |
| }(); |
| return 0; |
| #else |
| S<float> test; |
| int t_var = 0; |
| int vec[] = {1, 2}; |
| S<float> s_arr[] = {1, 2}; |
| S<float> &var = test; |
| |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute simd lastprivate(t_var, vec, s_arr, s_arr, var, var, svar) |
| for (int i = 0; i < 2; ++i) { |
| vec[i] = t_var; |
| s_arr[i] = var; |
| } |
| int i; |
| |
| return tmain<int>(); |
| #endif |
| } |
| |
| |
| // skip loop variables |
| |
| // copy from parameters to local address variables |
| |
| // load content of local address variables |
| // the distribute loop |
| // assignment: vec[i] = t_var; |
| |
| // assignment: s_arr[i] = var; |
| |
| // lastprivates |
| |
| |
| // template tmain |
| |
| |
| |
| // skip alloca of global_tid and bound_tid |
| // skip loop variables |
| |
| // skip init of bound and global tid |
| // copy from parameters to local address variables |
| |
| // load content of local address variables |
| // assignment: vec[i] = t_var; |
| |
| // assignment: s_arr[i] = var; |
| |
| // lastprivates |
| |
| |
| #endif |
| // CHECK1-LABEL: define {{[^@]+}}@main |
| // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 |
| // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) |
| // CHECK1-NEXT: ret i32 0 |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK1-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined |
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 |
| // CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] |
| // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: store double 1.000000e+00, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 |
| // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP18]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 |
| // CHECK1-NEXT: store ptr [[SFVAR7]], ptr [[TMP19]], align 8, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]]) |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK1-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK1: .omp.final.then: |
| // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK1: .omp.final.done: |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 |
| // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK1: .omp.lastprivate.then: |
| // CHECK1-NEXT: [[TMP25:%.*]] = load double, ptr [[G3]], align 8 |
| // CHECK1-NEXT: store volatile double [[TMP25]], ptr [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = load double, ptr [[TMP26]], align 8 |
| // CHECK1-NEXT: store volatile double [[TMP27]], ptr [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[SVAR6]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP28]], ptr [[TMP2]], align 4 |
| // CHECK1-NEXT: [[TMP29:%.*]] = load float, ptr [[SFVAR7]], align 4 |
| // CHECK1-NEXT: store float [[TMP29]], ptr [[TMP3]], align 4 |
| // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK1: .omp.lastprivate.done: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@main |
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 |
| // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) |
| // CHECK3-NEXT: ret i32 0 |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 |
| // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 |
| // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 |
| // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined |
| // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[_TMP5:%.*]] = alloca ptr, align 4 |
| // CHECK3-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] |
| // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: store double 1.000000e+00, ptr [[G3]], align 8, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP14]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: store i32 3, ptr [[SVAR6]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store ptr [[G3]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 |
| // CHECK3-NEXT: store ptr [[SVAR6]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 |
| // CHECK3-NEXT: store ptr [[SFVAR7]], ptr [[TMP19]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK3-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]]) |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK3-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK3: .omp.final.then: |
| // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK3: .omp.final.done: |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 |
| // CHECK3-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK3: .omp.lastprivate.then: |
| // CHECK3-NEXT: [[TMP25:%.*]] = load double, ptr [[G3]], align 8 |
| // CHECK3-NEXT: store volatile double [[TMP25]], ptr [[TMP0]], align 8 |
| // CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP27:%.*]] = load double, ptr [[TMP26]], align 4 |
| // CHECK3-NEXT: store volatile double [[TMP27]], ptr [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[SVAR6]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP28]], ptr [[TMP2]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = load float, ptr [[SFVAR7]], align 4 |
| // CHECK3-NEXT: store float [[TMP29]], ptr [[TMP3]], align 4 |
| // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK3: .omp.lastprivate.done: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@main |
| // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK5-NEXT: [[G1:%.*]] = alloca ptr, align 8 |
| // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK5-NEXT: store ptr [[G]], ptr [[G1]], align 8 |
| // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK5-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 |
| // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 |
| // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 |
| // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) |
| // CHECK5-NEXT: ret i32 0 |
| // |
| // |
| // CHECK7-LABEL: define {{[^@]+}}@main |
| // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK7-NEXT: entry: |
| // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK7-NEXT: [[G1:%.*]] = alloca ptr, align 4 |
| // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 |
| // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK7-NEXT: store ptr [[G]], ptr [[G1]], align 4 |
| // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 |
| // CHECK7-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 |
| // CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 |
| // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 |
| // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 |
| // CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) |
| // CHECK7-NEXT: ret i32 0 |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@main |
| // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK9-NEXT: [[G1:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: store ptr [[G]], ptr [[G1]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) |
| // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 |
| // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8 |
| // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP10]], align 8 |
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 8 |
| // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 8 |
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP13]], align 8 |
| // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 8 |
| // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP16]], align 8 |
| // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 8 |
| // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 8 |
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP19]], align 8 |
| // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK9-NEXT: store i64 [[TMP5]], ptr [[TMP20]], align 8 |
| // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK9-NEXT: store i64 [[TMP5]], ptr [[TMP21]], align 8 |
| // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP22]], align 8 |
| // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 3, ptr [[TMP25]], align 4 |
| // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK9-NEXT: store i32 5, ptr [[TMP26]], align 4 |
| // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8 |
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 8 |
| // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 8 |
| // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 8 |
| // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP31]], align 8 |
| // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP32]], align 8 |
| // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK9-NEXT: store i64 2, ptr [[TMP33]], align 8 |
| // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK9-NEXT: store i64 0, ptr [[TMP34]], align 8 |
| // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 |
| // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 4 |
| // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK9-NEXT: store i32 0, ptr [[TMP37]], align 4 |
| // CHECK9-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK9-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 |
| // CHECK9-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK9: omp_offload.failed: |
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]] |
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK9: omp_offload.cont: |
| // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() |
| // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done2: |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP41]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 |
| // CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined |
| // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK9: arrayctor.loop: |
| // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 |
| // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK9: arrayctor.cont: |
| // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) |
| // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 |
| // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK9: cond.true: |
| // CHECK9-NEXT: br label [[COND_END:%.*]] |
| // CHECK9: cond.false: |
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: br label [[COND_END]] |
| // CHECK9: cond.end: |
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK9: omp.inner.for.cond: |
| // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] |
| // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK9: omp.inner.for.cond.cleanup: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK9: omp.inner.for.body: |
| // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK9: omp.body.continue: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK9: omp.inner.for.inc: |
| // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1 |
| // CHECK9-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] |
| // CHECK9: omp.inner.for.end: |
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK9: omp.loop.exit: |
| // CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 |
| // CHECK9-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK9: .omp.final.then: |
| // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK9: .omp.final.done: |
| // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK9-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK9: .omp.lastprivate.then: |
| // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP0]], align 4 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP27]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done14: |
| // CHECK9-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP7]], align 8 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i64 4, i1 false) |
| // CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[SVAR8]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP29]], ptr [[TMP4]], align 4 |
| // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK9: .omp.lastprivate.done: |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done16: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK9-SAME: () #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) |
| // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8 |
| // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 8 |
| // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 8 |
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8 |
| // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8 |
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8 |
| // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP14]], align 8 |
| // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 8 |
| // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP17]], align 8 |
| // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 3, ptr [[TMP20]], align 4 |
| // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK9-NEXT: store i32 4, ptr [[TMP21]], align 4 |
| // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK9-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 8 |
| // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK9-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 |
| // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 8 |
| // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 8 |
| // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP26]], align 8 |
| // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8 |
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK9-NEXT: store i64 2, ptr [[TMP28]], align 8 |
| // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK9-NEXT: store i64 0, ptr [[TMP29]], align 8 |
| // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 |
| // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 |
| // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK9-NEXT: store i32 0, ptr [[TMP32]], align 4 |
| // CHECK9-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 |
| // CHECK9-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK9: omp_offload.failed: |
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] |
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK9: omp_offload.cont: |
| // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done2: |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP36]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store float 0.000000e+00, ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: store float [[TMP0]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK9-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined |
| // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK9-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK9: arrayctor.loop: |
| // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK9-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 |
| // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK9: arrayctor.cont: |
| // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) |
| // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 |
| // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK9: cond.true: |
| // CHECK9-NEXT: br label [[COND_END:%.*]] |
| // CHECK9: cond.false: |
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: br label [[COND_END]] |
| // CHECK9: cond.end: |
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] |
| // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK9: omp.inner.for.cond: |
| // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] |
| // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] |
| // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK9: omp.inner.for.cond.cleanup: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK9: omp.inner.for.body: |
| // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK9: omp.body.continue: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK9: omp.inner.for.inc: |
| // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK9-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] |
| // CHECK9: omp.inner.for.end: |
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK9: omp.loop.exit: |
| // CHECK9-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) |
| // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK9-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK9: .omp.final.then: |
| // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK9: .omp.final.done: |
| // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 |
| // CHECK9-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK9: .omp.lastprivate.then: |
| // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP26]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done13: |
| // CHECK9-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP7]], align 8 |
| // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i64 4, i1 false) |
| // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK9: .omp.lastprivate.done: |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done15: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 0, ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@main |
| // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK11-NEXT: [[G1:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: store ptr [[G]], ptr [[G1]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) |
| // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) |
| // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 |
| // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 4 |
| // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP10]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP11]], align 4 |
| // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP12]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP14]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP15]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP16]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP7]], ptr [[TMP18]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP19]], align 4 |
| // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP20]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP21]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 3, ptr [[TMP25]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK11-NEXT: store i32 5, ptr [[TMP26]], align 4 |
| // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 4 |
| // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP24]], ptr [[TMP28]], align 4 |
| // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP29]], align 4 |
| // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP30]], align 4 |
| // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP31]], align 4 |
| // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP32]], align 4 |
| // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK11-NEXT: store i64 2, ptr [[TMP33]], align 8 |
| // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK11-NEXT: store i64 0, ptr [[TMP34]], align 8 |
| // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 |
| // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP36]], align 4 |
| // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK11-NEXT: store i32 0, ptr [[TMP37]], align 4 |
| // CHECK11-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK11-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 |
| // CHECK11-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK11: omp_offload.failed: |
| // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]] |
| // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK11: omp_offload.cont: |
| // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() |
| // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done2: |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: ret i32 [[TMP41]] |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102 |
| // CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102.omp_outlined |
| // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 |
| // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK11: arrayctor.loop: |
| // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 |
| // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK11: arrayctor.cont: |
| // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) |
| // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 |
| // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK11: omp.inner.for.cond.cleanup: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP16]] |
| // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1 |
| // CHECK11-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 |
| // CHECK11-NEXT: br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK11: .omp.final.then: |
| // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK11: .omp.final.done: |
| // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK11-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK11: .omp.lastprivate.then: |
| // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP0]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP27]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK11: omp.arraycpy.body: |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK11: omp.arraycpy.done13: |
| // CHECK11-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP7]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i32 4, i1 false) |
| // CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[SVAR8]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP29]], ptr [[TMP4]], align 4 |
| // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK11: .omp.lastprivate.done: |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done15: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK11-SAME: () #[[ATTR1]] comdat { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) |
| // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) |
| // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP9]], align 4 |
| // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP10]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4 |
| // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP14]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP15]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP5]], ptr [[TMP16]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP17]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 3, ptr [[TMP20]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 |
| // CHECK11-NEXT: store i32 4, ptr [[TMP21]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 |
| // CHECK11-NEXT: store ptr [[TMP18]], ptr [[TMP22]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 |
| // CHECK11-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 |
| // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 |
| // CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP24]], align 4 |
| // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 |
| // CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP25]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP26]], align 4 |
| // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 |
| // CHECK11-NEXT: store ptr null, ptr [[TMP27]], align 4 |
| // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 |
| // CHECK11-NEXT: store i64 2, ptr [[TMP28]], align 8 |
| // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 |
| // CHECK11-NEXT: store i64 0, ptr [[TMP29]], align 8 |
| // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 |
| // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4 |
| // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 |
| // CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4 |
| // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 |
| // CHECK11-NEXT: store i32 0, ptr [[TMP32]], align 4 |
| // CHECK11-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, ptr [[KERNEL_ARGS]]) |
| // CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 |
| // CHECK11-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK11: omp_offload.failed: |
| // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]] |
| // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK11: omp_offload.cont: |
| // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done2: |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK11-NEXT: ret i32 [[TMP36]] |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store float 0.000000e+00, ptr [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[TMP0]], ptr [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK11-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined |
| // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK11-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 |
| // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK11: arrayctor.loop: |
| // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK11-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 |
| // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK11: arrayctor.cont: |
| // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) |
| // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1 |
| // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] |
| // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK11: omp.inner.for.cond.cleanup: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP15]] |
| // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK11-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0 |
| // CHECK11-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] |
| // CHECK11: .omp.final.then: |
| // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] |
| // CHECK11: .omp.final.done: |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 |
| // CHECK11-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] |
| // CHECK11: .omp.lastprivate.then: |
| // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK11: omp.arraycpy.body: |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP26]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK11: omp.arraycpy.done12: |
| // CHECK11-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP7]], align 4 |
| // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i32 4, i1 false) |
| // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] |
| // CHECK11: .omp.lastprivate.done: |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done14: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 0, ptr [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@main |
| // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK13-NEXT: [[G1:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 |
| // CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 |
| // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I16:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK13-NEXT: store ptr [[G]], ptr [[G1]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) |
| // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) |
| // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 |
| // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) |
| // CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8 |
| // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK13: arrayctor.loop: |
| // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 |
| // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK13: arrayctor.cont: |
| // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) |
| // CHECK13-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK13: omp.inner.for.cond.cleanup: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 |
| // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] |
| // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 |
| // CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK13: omp.body.continue: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP13]], 1 |
| // CHECK13-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) |
| // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK13: omp.arraycpy.body: |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR6]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK13: omp.arraycpy.done13: |
| // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 8 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) |
| // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 |
| // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] |
| // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK13: arraydestroy.body: |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK13: arraydestroy.done15: |
| // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() |
| // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN17]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] |
| // CHECK13: arraydestroy.body18: |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 |
| // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] |
| // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] |
| // CHECK13: arraydestroy.done22: |
| // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK13-NEXT: ret i32 [[TMP20]] |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK13-SAME: () #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 |
| // CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 |
| // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK13-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) |
| // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef signext 1) |
| // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 |
| // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) |
| // CHECK13-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 |
| // CHECK13-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8 |
| // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK13: arrayctor.loop: |
| // CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 |
| // CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK13: arrayctor.cont: |
| // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) |
| // CHECK13-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK13: omp.inner.for.cond.cleanup: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 |
| // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] |
| // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 |
| // CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK13: omp.body.continue: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP13]], 1 |
| // CHECK13-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) |
| // CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK13: omp.arraycpy.body: |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR6]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false) |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK13: omp.arraycpy.done13: |
| // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 8 |
| // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) |
| // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK13: arraydestroy.body: |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK13: arraydestroy.done15: |
| // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN16]], i64 2 |
| // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] |
| // CHECK13: arraydestroy.body17: |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] |
| // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 |
| // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] |
| // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] |
| // CHECK13: arraydestroy.done21: |
| // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] |
| // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK13-NEXT: ret i32 [[TMP19]] |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK13-NEXT: store float 0.000000e+00, ptr [[F]], align 4 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store float [[TMP0]], ptr [[F]], align 4 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK13-NEXT: store i32 0, ptr [[F]], align 4 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 |
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@main |
| // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK15-NEXT: [[G1:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 |
| // CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 |
| // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[I15:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK15-NEXT: store ptr [[G]], ptr [[G1]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) |
| // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00) |
| // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 |
| // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) |
| // CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 |
| // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 4 |
| // CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 4 |
| // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK15: arrayctor.loop: |
| // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 |
| // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK15: arrayctor.cont: |
| // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) |
| // CHECK15-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK15: omp.inner.for.cond: |
| // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] |
| // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] |
| // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK15: omp.inner.for.cond.cleanup: |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK15: omp.inner.for.body: |
| // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 |
| // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] |
| // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK15: omp.body.continue: |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK15: omp.inner.for.inc: |
| // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], 1 |
| // CHECK15-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] |
| // CHECK15: omp.inner.for.end: |
| // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) |
| // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] |
| // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK15: omp.arraycpy.body: |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR6]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] |
| // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK15: omp.arraycpy.done12: |
| // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) |
| // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] |
| // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK15: arraydestroy.body: |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK15: arraydestroy.done14: |
| // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() |
| // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 |
| // CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN16]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] |
| // CHECK15: arraydestroy.body17: |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 |
| // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] |
| // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] |
| // CHECK15: arraydestroy.done21: |
| // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK15-NEXT: ret i32 [[TMP20]] |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK15-SAME: () #[[ATTR1]] comdat { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 |
| // CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 |
| // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK15-NEXT: store i32 0, ptr [[T_VAR]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) |
| // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1) |
| // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 |
| // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) |
| // CHECK15-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 |
| // CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4 |
| // CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 4 |
| // CHECK15-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 4 |
| // CHECK15-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 4 |
| // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 |
| // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 |
| // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 |
| // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] |
| // CHECK15: arrayctor.loop: |
| // CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] |
| // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) |
| // CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 |
| // CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] |
| // CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] |
| // CHECK15: arrayctor.cont: |
| // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) |
| // CHECK15-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK15: omp.inner.for.cond: |
| // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] |
| // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] |
| // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK15: omp.inner.for.cond.cleanup: |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK15: omp.inner.for.body: |
| // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 |
| // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] |
| // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK15: omp.body.continue: |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK15: omp.inner.for.inc: |
| // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP13]], 1 |
| // CHECK15-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] |
| // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] |
| // CHECK15: omp.inner.for.end: |
| // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 |
| // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) |
| // CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] |
| // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK15: omp.arraycpy.body: |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR6]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false) |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]] |
| // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK15: omp.arraycpy.done12: |
| // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 4 |
| // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) |
| // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK15: arraydestroy.body: |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK15: arraydestroy.done14: |
| // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN15]], i32 2 |
| // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] |
| // CHECK15: arraydestroy.body16: |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] |
| // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 |
| // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] |
| // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] |
| // CHECK15: arraydestroy.done20: |
| // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] |
| // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 |
| // CHECK15-NEXT: ret i32 [[TMP19]] |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK15-NEXT: store float 0.000000e+00, ptr [[F]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: store float [[TMP0]], ptr [[F]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK15-NEXT: store i32 0, ptr [[F]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 |
| // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 |
| // CHECK15-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
| // |
| // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK15-NEXT: entry: |
| // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 |
| // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 |
| // CHECK15-NEXT: ret void |
| // |
