| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals --include-generated-funcs |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV |
| |
| int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; } |
| int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; } |
| int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; } |
| int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; } |
| int foo() { |
| return ftc() + ftc_def() + ftc_dup1() + ftc_dup2(); |
| } |
| |
| inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; } |
| inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void); |
| inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; } |
| |
| int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; } |
| |
| int __attribute__((target_clones("default"))) main() { |
| return ftc_inline1() + ftc_inline2() + ftc_inline3() + ftc_direct(); |
| } |
| inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))) ftc_inline2(void) { return 2; }; |
| |
| |
| // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } |
| // CHECK: @ftc.ifunc = weak_odr ifunc i32 (), ptr @ftc.resolver |
| // CHECK: @ftc_def.ifunc = weak_odr ifunc i32 (), ptr @ftc_def.resolver |
| // CHECK: @ftc_dup1.ifunc = weak_odr ifunc i32 (), ptr @ftc_dup1.resolver |
| // CHECK: @ftc_dup2.ifunc = weak_odr ifunc i32 (), ptr @ftc_dup2.resolver |
| // CHECK: @ftc_inline1.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver |
| // CHECK: @ftc_inline2.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver |
| // CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver |
| |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc._MlseMaes( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc._Msve2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // CHECK-LABEL: @ftc.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc._MlseMaes |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc._Msve2 |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @ftc |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_def._Msha2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_def._Msha2Mmemtag2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_def( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK-LABEL: @ftc_def.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_def._Msha2Mmemtag2 |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc_def._Msha2 |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @ftc_def |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_dup1._Msha2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_dup1( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // CHECK-LABEL: @ftc_dup1.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_dup1._Msha2 |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @ftc_dup1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_dup2._Mfp( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_dup2._MdotprodMcrc( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_dup2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK-LABEL: @ftc_dup2.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1040 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1040 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_dup2._MdotprodMcrc |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 256 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc_dup2._Mfp |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @ftc_dup2 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @foo( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc.ifunc() |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 @ftc_def.ifunc() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1.ifunc() |
| // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2.ifunc() |
| // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NEXT: ret i32 [[ADD5]] |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_direct( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @main( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1.ifunc() |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2.ifunc() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3.ifunc() |
| // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() |
| // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NEXT: ret i32 [[ADD5]] |
| // CHECK-LABEL: @ftc_inline1.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc_inline1._MrcpcMpredres |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513 |
| // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 513 |
| // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] |
| // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @ftc_inline1._MrngMsimd |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @ftc_inline1 |
| // CHECK-LABEL: @ftc_inline2.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65536 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc_inline2._Mfp16 |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @ftc_inline2 |
| // CHECK-LABEL: @ftc_inline3.resolver( |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @ftc_inline3._MsveMsb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @ftc_inline3._Mbti |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @ftc_inline3 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline1._MrngMsimd( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline1._MrcpcMpredres( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline1._Msve2-aesMwfxt( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline1( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline2._Mfp16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline2._MfcmaMsve2-bitperm( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline2( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline3._Mbti( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline3._MsveMsb( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: @ftc_inline3( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @ftc( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @ftc_def( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 1 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @ftc_dup1( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 2 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @ftc_dup2( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 3 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @foo( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @ftc() |
| // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @ftc_def() |
| // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @ftc_dup1() |
| // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NOFMV-NEXT: [[CALL4:%.*]] = call i32 @ftc_dup2() |
| // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NOFMV-NEXT: ret i32 [[ADD5]] |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @ftc_direct( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 4 |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: @main( |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK-NOFMV-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @ftc_inline1() |
| // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @ftc_inline2() |
| // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @ftc_inline3() |
| // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NOFMV-NEXT: [[CALL4:%.*]] = call i32 @ftc_direct() |
| // CHECK-NOFMV-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NOFMV-NEXT: ret i32 [[ADD5]] |
| |
| // CHECK: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" } |
| // CHECK: attributes #1 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" } |
| // CHECK: attributes #2 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } |
| // CHECK: attributes #3 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" } |
| // CHECK: attributes #4 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" } |
| // CHECK: attributes #5 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" } |
| // CHECK: attributes #6 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" } |
| // CHECK: attributes #7 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" } |
| // CHECK: attributes #8 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" } |
| // CHECK: attributes #9 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" } |
| // CHECK: attributes #10 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" } |
| // CHECK: attributes #11 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" } |
| // CHECK: attributes #12 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" } |
| // CHECK: attributes #13 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" } |
| |
| // CHECK-NOFMV: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } |
| // CHECK-NOFMV: attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" } |