| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // REQUIRES: riscv-registered-target |
| // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ |
| // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ |
| // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s |
| |
| #include <riscv_vector.h> |
| |
| // Use constexpr function to make sure we correctly evaluate it as a constant |
| // when emitting IR for the vget/vset builtins. |
| constexpr int foo() { return 1; } |
| |
| // CHECK-RV64-LABEL: @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8) |
| // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] |
| // |
| vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) { |
| return __riscv_vget_v_i8m2_i8m1(src, foo()); |
| } |
| |
| // CHECK-RV64-LABEL: @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8) |
| // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] |
| // |
| vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) { |
| return __riscv_vset_v_i8m1_i8m2(dest, foo(), val); |
| } |
